Amplifier used to improve operational performance under bypass mode

• US 10,326,412 B2
• Filed: 06/14/2018
• Issued: 06/18/2019
• Est. Priority Date: 03/28/2016
• Status: Active Grant

• Current Assignee: RichWave Technology Corp
• Original Assignee: RichWave Technology Corp
• Inventors: Chen, Chih-Sheng, Chen, Chang-Yi
• Primary Examiner(s): Choe, Henry
• Application Number:
  US16/008,054
• Publication Number:
  US 20180294778A1
• Time in Patent Office: 369 Days
• Field of Search: 330296, 330311, 330285, 330 85
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 2203/7239 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers and shunting lines by one or more switch(es)
• CPC Class Codes: H03F 3/16 with field-effect devices
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

An amplifier includes an input terminal for receiving an input signal, an output terminal for outputting an output signal, a first transistor, a second transistor having a first terminal coupled to a second terminal of the first transistor, a third transistor having a first terminal coupled to a second terminal of the second transistor, a capacitor coupled between a control terminal and a second terminal of the third transistor, a bias circuit coupled to the first terminal of the third transistor for providing a bias voltage to the third transistor, a fourth transistor having a first terminal coupled to the input terminal and a second terminal coupled to the output terminal for providing a bypass path, and a fifth transistor having a first terminal coupled to the first terminal of the first transistor and a second terminal coupled to the output terminal.

Claims

1. An amplifier comprising:

an input terminal configured to receive an input signal;

an output terminal configured to transmit an output signal corresponding to the input signal;

a first transistor comprising a control terminal, a first terminal, and a second terminal;

a second transistor comprising a first terminal coupled to the second terminal of the first transistor, a control terminal, and a second terminal;

a third transistor comprising a first terminal coupled to the second terminal of the second transistor, a control terminal, and a second terminal;

a bias circuit comprising a first terminal coupled to the first terminal of the third transistor, and a second terminal configured to provide a bias voltage to the first terminal of the third transistor;

a fourth transistor comprising a first terminal coupled to the input terminal, and a second terminal coupled to the output terminal; and

a fifth transistor comprising a first terminal coupled to the first terminal of the first transistor, a control terminal, and a second terminal coupled to the output terminal.

2. The amplifier of claim 1, wherein the bias circuit includes a diode, the first terminal of the bias circuit is a cathode of the diode, and the second terminal of the bias circuit is an anode of the diode.

3. The amplifier of claim 1, further comprising a first impedance unit coupled between the first terminal of the bias circuit and the first terminal of the third transistor.

4. The amplifier of claim 1, further comprising:

a sixth transistor comprising a first terminal coupled to a reference voltage source, a control terminal, and a second terminal coupled to the control terminal of the first transistor.

5. The amplifier of claim 4, further comprising:

a third bias unit coupled to the second terminal of the first transistor and configured to provide a third bias voltage to the second terminal of the first transistor.

6. The amplifier of claim 4, further comprising a first bias unit coupled to the first terminal of the first transistor and configured to provide a first bias voltage to the first terminal of the first transistor.

7. The amplifier of claim 6, wherein the first bias unit comprising:

a seventh transistor comprising a first terminal coupled to the first terminal of the first transistor, a control terminal and a second terminal; and

a second impedance unit and/or a second match unit coupled between the first terminal of the seventh transistor and the first terminal of the first transistor.

8. The amplifier of claim 4, further comprising:

a first capacitor comprising a first terminal coupled to the reference voltage source and a second terminal coupled to the first terminal of the sixth transistor; and

/or

a third impedance unit coupled to the second terminal of the sixth transistor.

9. The amplifier of claim 1, further comprising a control unit comprising:

an eighth transistor comprising a first terminal coupled to the control terminal of the second transistor, a control terminal, and a second terminal coupled to the input terminal;

a second bias unit coupled to the second terminal of the eighth transistor and configured to provide a second bias voltage to the second terminal of the eighth transistor; and

a second capacitor coupled between the second terminal of the eighth transistor and the input terminal.

10. The amplifier of claim 1, further comprising:

a third bias unit coupled to the second terminal of the first transistor and configured to provide a third bias voltage to the second terminal of the first transistor.

11. The amplifier of claim 1, wherein the control terminal of the second transistor is coupled to the input terminal.

12. The amplifier of claim 1, wherein the amplifier enters a second mode from a first mode when an intensity of the input signal is greater than a threshold.

13. The amplifier of claim 1, further comprising:

a third capacitor comprising a first terminal coupled to the control terminal of the third transistor, and a second terminal coupled to the second terminal of the third transistor.