Level shifter circuit to minimize duty-cycle distortion on clock paths

• US 10,326,431 B1
• Filed: 03/30/2018
• Issued: 06/18/2019
• Est. Priority Date: 03/30/2018
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Patel, Pratik Rajeshbhai, Marfatia, Percy Tehmul, Narayanan, Rajagopal
• Primary Examiner(s): Nguyen, Long
• Application Number:
  US15/941,055
• Time in Patent Office: 445 Days
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration
• CPC Class Codes: H03K 3/356182 with additional means for controlling the main nodes

Abstract

A novel clock level-shifter to reduce duty-cycle distortion across wide input-output voltage operating range is disclosed. In some implementations, a level shifter includes an input stage coupled to a first power supply to receive an input signal, an output stage coupled to a second power supply to generate an output signal, and a first switch coupled directly between the output stage and the second power supply, wherein the input signal turns on or off the first switch. In some implementations, the first switch has a gate, a source, and a drain, the source being coupled to the second power supply, the drain being coupled to the output stage, and the gate being driven directly by the input signal.

Claims

1. A level shifter, comprising:

an input stage coupled to a first power supply of a first power domain to receive an input signal;

an output stage coupled to a second power supply of a second power domain to generate an output signal;

a first switch coupled directly between the output stage and the second power supply, wherein the input signal controls the first switch to enhance discharging of a source of a first pull-up transistor of the output stage;

a latch in the second power domain, the latch being coupled between the input stage and the output stage; and

a bypass switch coupled between the output stage and the latch, wherein the bypass switch is controlled by a delayed version of the input signal to initiate charging of a gate of the first pull-up transistor of the output stage.

2. The level shifter of claim 1, wherein the first switch has a gate, a source, and a drain, the source being coupled to the second power supply, the drain being coupled to the output stage, and the gate being driven directly by the input signal.

3. The level shifter of claim 2, wherein the first switch comprises a first p-type transistor.

4. The level shifter of claim 3, wherein the output stage comprises:

a second p-type transistor having a gate, a source, and a drain, the source of the second p-type transistor coupled to the drain of the first p-type transistor; and

a first n-type transistor having a gate, a source, and a drain, the gate of the first n-type transistor coupled to the gate of the second p-type transistor, and the drain of the first n-type transistor coupled to the drain of the second p-type transistor.

5. The level shifter of claim 4, wherein the first switch is configured to turn on and to cause the second p-type transistor to start charging in response to the input signal going low.

6. The level shifter of claim 1, wherein the bypass switch has a gate, a source, and a drain, the drain being coupled to the second power supply, the source being coupled to an input of the output stage, and the gate being coupled to the latch.

7. The level shifter of claim 6, wherein the input stage comprises:

a first inverter having an input and an output, wherein the input is configured to receive the input signal; and

a second inverter having an input and an output, wherein the input of the second inverter is coupled to the output of the first inverter, and the output of the second inverter is coupled to the gate of the bypass switch.

8. The level shifter of claim 7, wherein the bypass switch comprises an n-type transistor.

9. The level shifter of claim 1, wherein the first power supply is lower than the second power supply.

10. A method to level shift an input signal, comprising:

receiving the input signal at an input stage in a first power domain associated with a first power supply;

generating an output signal at an output stage in a second power domain associated with a second power supply;

using the input signal to directly control a first switch in the output stage to enhance discharging of a source of a first pull-up transistor of the output stage;

providing a latch in the second power domain to store a value corresponding to the input signal; and

using a delayed version of the input signal to control a bypass switch to initiate charging of a gate of the first pull-up transistor of the output stage.

11. The method of claim 10, wherein the first switch comprises a p-type transistor having a gate, a source, and a drain, and using the input signal to directly control the first switch comprises applying the input signal to the gate of the p-type transistor.

12. The method of claim 11, further comprising coupling the source of the p-type transistor to the second power supply.

13. The method of claim 10, wherein the first power supply is lower than the second power supply.