Methods and systems for providing multi-stage distributed decision feedback equalization
First Claim
1. A method comprising:
- pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising (i) a set of data signal nodes and (ii) a set of decision feedback equalization (DFE) correction nodes;
in response to a sampling clock, generating a differential data voltage signal by discharging the set of data signal nodes according to a received differential input voltage signal and generating an aggregate differential DFE correction signal by discharging the set of DFE correction nodes according to a summation of a plurality of DFE correction factors; and
generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock.
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Abstract
Pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising a set of data signal nodes and a set of DFE correction nodes, in response to a sampling clock, generating a differential data voltage and an aggregate differential DFE correction signal, and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock.
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Citations
20 Claims
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1. A method comprising:
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pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising (i) a set of data signal nodes and (ii) a set of decision feedback equalization (DFE) correction nodes; in response to a sampling clock, generating a differential data voltage signal by discharging the set of data signal nodes according to a received differential input voltage signal and generating an aggregate differential DFE correction signal by discharging the set of DFE correction nodes according to a summation of a plurality of DFE correction factors; and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus comprising:
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a discrete time-integration stage comprising two or more sets of nodes, the two or more sets of nodes comprising (i) a set of data signal nodes and (ii) a set of decision feedback equalization (DFE) correction nodes, the discrete time-integration stage configured to; pre-charge the two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state; and generate, in response to a sampling clock, a differential data voltage signal by discharging the set of data signal nodes according to a received differential input voltage signal and an aggregate differential DFE correction signal by discharging the set of DFE correction nodes according to a summation of a plurality of DFE correction factors; and the multi-input summation latch configured to generate a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal, the multi-input summation latch configured to subsequently hold the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification