Clock recovery and data recovery for programmable logic devices
First Claim
1. A method comprising:
- receiving a serial data stream;
measuring payload time periods between signal transitions in a payload portion of the serial data stream using at least one Grey code oscillator; and
generating a recovered data signal corresponding to the payload portion of the serial data stream by, at least in part, comparing the measured payload time periods to one or more calibration time periods.
3 Assignments
0 Petitions
Accused Products
Abstract
Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.
-
Citations
21 Claims
-
1. A method comprising:
-
receiving a serial data stream; measuring payload time periods between signal transitions in a payload portion of the serial data stream using at least one Grey code oscillator; and generating a recovered data signal corresponding to the payload portion of the serial data stream by, at least in part, comparing the measured payload time periods to one or more calibration time periods. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A computer-implemented method comprising:
-
detecting, in a design for a programmable logic device (PLD), a serial data stream input and a deserializer block configured to generate a recovered data signal corresponding to a payload portion of a serial data stream provided by the serial data stream input; and synthesizing the design into a plurality of PLD components, wherein the plurality of PLD components are configured to implement; a Grey code oscillator for the deserializer block in the design, wherein the Grey code oscillator is configured to measure payload time periods between signal transitions in the payload portion of the serial data stream provided by the serial data stream input; and at least one comparator for the deserializer block in the design, wherein the at least one comparator is configured to compare the measured payload time periods provided by the Grey code oscillator to one or more calibration time periods to generate the recovered data signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
-
Specification