Technologies for enhancing computer security

• US 10,326,757 B2
• Filed: 08/01/2018
• Issued: 06/18/2019
• Est. Priority Date: 05/14/2013
• Status: Active Grant

• Current Assignee: Kara Partners LLC
• Original Assignee: Kara Partners LLC
• Inventors: Penny, Brian, Penny, Desmond
• Primary Examiner(s): Tabor, Amare F
• Application Number:
  US16/051,794
• Publication Number:
  US 20180343244A1
• Time in Patent Office: 321 Days
• Field of Search: 726 7, 726 26, 726 2, 713168, 380 28, 380 42
• CPC Class Codes: G06F 21/31 User authentication
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/725 operating on a secure reference time value
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 2221/2105 Dual mode as a secondary aspect
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: G06F 2221/2151 Time stamp
• CPC Class Codes: H03M 7/08 the radix being ten, i.e. pure decimal code
• CPC Class Codes: H04K 1/003 by varying carrier frequency at or within predetermined or random intervals H04K1/04 takes precedence
• CPC Class Codes: H04K 1/06 by transmitting the information or elements thereof at unnatural speeds or in jumbled order or backwards
• CPC Class Codes: H04L 63/00 Network architectures or network communication protocols for network security cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00; network architectures or network communication protocols for wireless network security H04W12/00; security arrangements for protecting computers or computer systems against unauthorised activity G06F21/00
• CPC Class Codes: H04L 63/0428 wherein the data content is protected, e.g. by encrypting or encapsulating the payload
• CPC Class Codes: H04L 63/083 using passwords cryptographic mechanisms or cryptographic arrangements for entity authentication using a predetermined code H04L9/3226
• CPC Class Codes: H04L 67/06 specially adapted for file transfer, e.g. file transfer protocol [FTP]
• CPC Class Codes: H04L 9/06 the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
• CPC Class Codes: H04L 9/0618 Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
• CPC Class Codes: H04L 9/12 Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
• CPC Class Codes: H04L 9/3226 using a predetermined code, e.g. password, passphrase or PIN network architectures or network communication protocols for supporting authentication of entities using passwords in a packet data network H04L63/083

Abstract

A system including: at least one processor; and at least one memory, having stored thereon computer program code that, when executed by the at least one processor, controls the at least one processor to: receive a first sequence of values; segment the first sequence of values into a first subsequence having a first length and a second subsequence having a second length; modify the first subsequence by inserting one or more values into the first subsequence to create a modified first subsequence of a third length; modify the second subsequence by one or more inserting values into the second subsequence to create a modified second subsequence of the third length; combine the modified first subsequence and the modified second subsequence to create a second sequence of values; and output the second sequence of values.

Claims

1. A system comprising:

at least one processor; and

at least one memory, having stored thereon computer program code that, when executed by the at least one processor, controls the at least one processor to;

receive a first sequence of values;

segment the first sequence of values into a plurality of first subsequences each having a first length and a plurality of second subsequences each having a second length;

modify each of the plurality of first subsequences by inserting one or more values into each of the plurality of first subsequences to create a plurality of modified first subsequences each having a third length;

modify each of the plurality of second subsequences by inserting one or more values into each of the plurality of second subsequences to create a plurality of modified second subsequences each having the third length;

combine the plurality of modified first subsequences and the plurality of modified second subsequences to create a second sequence of values; and

output the second sequence of values.

2. The system of claim 1, wherein the computer program code, when executed by the at least one processor, further controls the at least one processor to output the second sequence of values for transmission to a destination device.

3. The system of claim 2, wherein the first, second, and third lengths are known by the destination device.

4. The system of claim 1, wherein the computer program code, when executed by the at least one processor, further controls the at least one processor to modify the first, second, and third lengths as a function of time.

5. The system of claim 1, wherein the computer program code, when executed by the at least one processor, further controls the at least one processor to:

receive a third sequence of values;

segment the third sequence of values into a third subsequence and a fourth subsequence each having a fourth length;

modify the third subsequence by removing one or more values from the third subsequence to create a modified third subsequence of a fifth length;

modify the fourth subsequence by removing one or more values from the fourth subsequence to create a modified fourth subsequence of a sixth length; and

combine the modified third subsequence and the modified fourth subsequence to create a fourth sequence of values.

6. The system of claim 1, wherein the computer program code, when executed by the at least one processor, further controls the at least one processor to:

receive a third sequence of values;

segment the third sequence of values into a plurality of third subsequences and a plurality of fourth subsequences each having a fourth length;

modify each of the plurality of third subsequences by removing one or more values from each of the plurality of third subsequences to create a plurality of modified third subsequences each having a fifth length;

modify each of the plurality of fourth subsequences by removing one or more values from each of the plurality of fourth subsequences to create a plurality of modified fourth subsequences each having a sixth length; and

combining the plurality of modified third subsequences and the plurality of modified fourth subsequences to create a fourth sequence of values.

7. The system of claim 5, wherein the fourth length is the same as the third length, the fifth length is the same as the first length, the sixth length is the same as the second length, and the fourth sequence of values is identical to the first sequence of values.

8. The system of claim 1, further comprising a switch configured to switch between a first mode and a second mode,

wherein the computer program code, when executed by the at least one processor, further controls the at least one processor to:

segment the first sequence of values into the plurality of first subsequences each having the first length based on the switch being in the first mode, and

segment the first sequence of values into the plurality of second subsequences each having the second length based on the switch being in the second mode.

9. A system comprising a plurality of circuits configured to:

receive a first sequence of values;

segment the first sequence of values into a plurality of first subsequences each having a first length and a plurality of second subsequences each having a second length;

modify each of the plurality of first subsequences by inserting one or more values into each of the plurality of first subsequences to create a plurality of modified first subsequences each having of a third length;

modify each of the plurality of second subsequences by inserting one or more values into each of the plurality of second subsequences to create a plurality of modified second subsequences of the third length;

combine the plurality of modified first subsequences and the plurality of modified second subsequences to create a second sequence of values; and

output the second sequence of values.

10. The system of claim 9, wherein the outputting comprises outputting the second sequence of values for transmission to a destination device.

11. The system of claim 10, wherein the first, second, and third lengths are known by the destination device.

12. The system of claim 9 further comprising selecting at least one of the first, second, and third lengths as a function of time.

13. The system of claim 9, wherein the plurality of circuits are further configured to recreate the first sequence of values by:

receiving a third sequence of values;

segmenting the third sequence of values into a third subsequence and a fourth subsequence each having the third length;

modifying the third subsequence by removing one or more values from the third subsequence to create a modified third subsequence of the first length;

modify the fourth subsequence by removing one or more values from the fourth subsequence to create a modified fourth subsequence of the second length; and

combining the modified third subsequence and the modified fourth subsequence to recreate the first sequence of values.

14. The system of claim 9, wherein the plurality of circuits are further configured to recreate the first sequence of values by:

receiving, at the processor, a third sequence of values;

segmenting, by the processor, the third sequence of values into a plurality of third subsequences and a plurality of fourth subsequences each having a fourth length;

modifying, by the processor, each of the plurality of third subsequences by removing one or more values from each of the plurality of third subsequences to create a plurality of modified third subsequences each having a fifth length;

modifying, by the processor, each of the plurality of fourth subsequences by removing one or more values from each of the plurality of fourth subsequences to create a plurality of modified fourth subsequences each having a sixth length; and

combining, by the processor, the plurality of modified third subsequences and the plurality of modified fourth subsequences to recreate the first sequence of values.

15. The system of claim 9, wherein the plurality of circuits are further configured to output, after outputting the second sequence of values, a third sequence of values comprising random values.

16. the system of claim 9, further comprising a switch configured to switch between a first mode and a second mode,

wherein the plurality of circuits are configured to:

segment the first sequence of values into the plurality of first subsequences each having the first length based on the switch being in the first mode, and

segment the first sequence of values into the plurality of second subsequences each having the second length based on the switch being in the second mode.

17. A system comprising a plurality of circuits configured to:

receive a first sequence of values;

segment the first sequence of values into a plurality of first subsequences and a plurality of second subsequences each having a first length;

modify each of the plurality of first subsequences by removing one or more values from each of the plurality of first subsequences to create a plurality of modified first subsequences each having a second length;

modify each of the plurality of second subsequences by removing one or more values from each of the plurality of second subsequences to create a plurality of modified second subsequences each having a third length; and

combine the modified first subsequence and the modified second subsequence to create a second sequence of values.

18. The system of claim 17, wherein the first sequence of values is encrypted, and the second sequence of values is unencrypted.

19. The system of claim 17, wherein the plurality of circuits are further configured to:

receive the first sequence of values from a source device; and

output the second sequence of values to a destination device.

20. The system of claim 17, wherein at least one of the first, second, and third lengths changes as a function of time.