Wafer level package and method of manufacturing the same

• US 10,329,142 B2
• Filed: 04/05/2016
• Issued: 06/25/2019
• Est. Priority Date: 12/18/2015
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Lee, Moon Chul, Kim, Duck Hwan, Lee, Yeong Gyu, Lee, Jae Chang, Kim, Tae Yoon, Min, Kyong Bok
• Primary Examiner(s): Parker, Allen L
• Assistant Examiner(s): Ausar-El, Charles N
• Application Number:
  US15/091,057
• Publication Number:
  US 20170174503A1
• Time in Patent Office: 1,176 Days
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 23/00 Details of semiconductor or other solid state devices H01L25/00 takes precedence ; structural arrangements for testing or measuring during manufacture or treatment, or for reliability measurements H01L22/00; arrangements for connecting or disconnecting semiconductor or solid-state bodies, or methods related thereto H01L24/00; finger print sensors G06V40/12
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP

Abstract

A wafer level package includes a wafer member having inner cavities in which circuit elements are disposed, element wall members disposed on an internal surface of the wafer member and enclosing element sections in which the circuit elements are disposed, and clearance wall members disposed on external surfaces of the element wall members and dividing a space between the element sections into clearance sections.

Claims

1. A wafer level package comprising:

a wafer member having inner cavities in which a circuit element is disposed;

an element wall member extending vertically on an internal surface of the wafer member and enclosing an element section in which the circuit element is disposed, the element section spaced apart horizontally from an adjacent element section by a dicing space; and

a clearance wall member extending horizontally from an external surface of the element section across the dicing space to an external surface of the adjacent element section to divide the dicing space between the element sections into clearance sections isolated each from the other.

2. The wafer level package of claim 1, wherein the wafer member comprises a cap wafer and a device wafer coupled to the cap wafer to form the inner cavities, and

the clearance wall member protrudes from an internal surface of at least one of the cap wafer and the device wafer.

3. The wafer level package of claim 1, wherein the clearance wall member protrudes from the internal surface of the wafer member and forms a stepped shape.

4. The wafer level package of claim 1, wherein the clearance wall member protrudes from the internal surface of the wafer member and forms a tapered shape.

5. The wafer level package of claim 1, wherein the element wall member enclosing the circuit element has a prismatic shape.

6. The wafer level package of claim 1, wherein the circuit element is connected to the element wall member.

7. The wafer level package of claim 1, wherein the circuit element corresponds to a bulk acoustic wave (BAW) resonator.

8. The wafer level package of claim 1, wherein the element section is spaced apart from the adjacent element section by two element wall member thicknesses and one clearance wall length.

9. The wafer level package of claim 1, wherein the clearance wall is disposed between adjacent clearance sections.

10. A wafer level package comprising:

a first wafer and a second wafer with a vertical space therebetween;

first wall members that allocate a portion of the vertical space as element sections, the element sections each comprising one or more circuit elements, and each element section spaced apart from an adjacent element section by a horizontal channel space between external surfaces of the first wall members; and

second wall members, each extending from a first wall member across the horizontal channel space between adjacent element sections to an adjacent first wall member of the adjacent element section to divide a portion of the horizontal channel space external to the element sections into clearance sections isolated each from the other.

11. The wafer level package of claim 10, wherein the portion of the horizontal channel space external to the element sections comprises a clearance area on a device wafer where no circuit elements are disposed.

12. The wafer level package of claim 10, wherein the first wall members hermetically seal each element section, and the second wall members seal each clearance section.

13. The wafer level package of claim 10, wherein at least a portion of the first wall members and at least a portion of the second wall members are formed integrally with either the first wafer or the second wafer.

14. The wafer level package of claim 10, wherein

a first portion of the first wall members and a first portion of the second wall members are formed to protrude from the first wafer;

a second portion of the first wall members and a second portion of the second wall members are formed to protrude from the second wafer; and

the first portion of the first wall members and the first portion of the second wall members are, respectively, bonded to the second portion of the first wall members and the second portion of the second wall members to seal the element sections and the clearance sections.

15. The wafer level package of claim 10, wherein the first wall members and the second wall members define element wall members and clearance wall members, respectively.

16. The wafer level package of claim 10, wherein the first wafer comprises a device wafer and the second wafer comprises a cap wafer.

17. The wafer level package of claim 10, wherein each second wall is disposed between adjacent clearance sections.

18. A semiconductor device, comprising:

a circuit element disposed on a device substrate;

an element wall member extending vertically between the device substrate and a cap substrate and enclosing an element section in which the circuit element is disposed; and

a clearance wall member extending horizontally from an external surface of the element wall member,

wherein the clearance wall member comprises a portion protruding from the device substrate or the cap substrate.