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Wafer level package and method of manufacturing the same

  • US 10,329,142 B2
  • Filed: 04/05/2016
  • Issued: 06/25/2019
  • Est. Priority Date: 12/18/2015
  • Status: Active Grant
First Claim
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1. A wafer level package comprising:

  • a wafer member having inner cavities in which a circuit element is disposed;

    an element wall member extending vertically on an internal surface of the wafer member and enclosing an element section in which the circuit element is disposed, the element section spaced apart horizontally from an adjacent element section by a dicing space; and

    a clearance wall member extending horizontally from an external surface of the element section across the dicing space to an external surface of the adjacent element section to divide the dicing space between the element sections into clearance sections isolated each from the other.

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