Scalable data access system and methods of eliminating controller bottlenecks

• US 10,331,353 B2
• Filed: 04/08/2017
• Issued: 06/25/2019
• Est. Priority Date: 04/08/2016
• Status: Active Grant

• Current Assignee: Branislav Radovanovic
• Original Assignee: Branislav Radovanovic
• Inventors: Radovanovic, Branislav
• Primary Examiner(s): Dudek, Jr., Edward J
• Application Number:
  US15/482,726
• Publication Number:
  US 20170293428A1
• Time in Patent Office: 808 Days
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/263 Network storage, e.g. SAN or NAS
• CPC Class Codes: G06F 2212/286 Mirrored cache memory
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data access system has host computers having front-end controllers nFE_SAN connected via a bus or network interconnect to back-end storage controllers nBE_SAN, and physical disk drives connected via network interconnect to the nBE_SANs to provide a distributed, high performance, policy based or dynamically reconfigurable, centrally managed, data storage acceleration system. The hardware and software architectural solutions eliminate BE_SAN controller bottlenecks and improve performance and scalability. In an embodiment, the nBE_SAN (BE_SAN) firmware recognize controller overload conditions, informs Distributed Resource Manager (DRM), and, based on the DRM provided optimal topology information, delegates part of its workload to additional controllers. The nFE_SAN firmware and additional hardware using functionally independent and redundant CPUs and memory that mitigate single points of failure and accelerates write performance. The nFE_SAN and FE_SAN controllers facilitate Converged I/O Interface by simultaneously supporting storage I/O and network traffic.

Claims

1. A computing system of the type comprising at least one processor (CPU) coupled through at least one front-end storage controller (nFE_SAN) to a first and second storage-area network (SAN), the first and second SAN coupled through at least one back-end storage controller (nBE_SAN) to a plurality of storage devices, the improvement comprising:

a first nFE_SAN of the at least one nFE_SAN having a first and a second write-back cache module configured to, upon receiving a write command addressed to a data block, to receive write data from the at least one CPU, maintain a first copy of the write data in the first write-back cache module and a second copy of the write data in the second write-back cache module of data written by the at least one processor to the storage devices until the data is written to the at least one nBE_SAN, the first write-back cache module configured to receive power from a first power supply and the second write-back cache module configured to receive power from a second power supply;

the first nFE_SAN coupled to the at least one nBE_SAN through a first SAN and through a second SAN, the first SAN independent of the second SAN;

the nFE_SAN configured to be capable of transmitting data from the first write-back cache module to the at least one nBE_SAN over the first SAN when the first power supply is operational, and capable of transmitting data from the second write-back cache module to the at least one nBE_SAN when the second power supply is operational and the first power supply not operational; and

the nFE_SAN configured to provide a write command complete response to the at least one CPU upon receiving the write data into the first and second writeback cache.

2. The computing system of claim 1 wherein the nFE_SAN is configured to request a write data lock from the at least one nBE_SAN for the data block upon receiving the write command, and to provide the write command complete response to the at least one CPU upon receiving the write data into the first and second writeback cache and receiving a write data lock from the at least one nBE_SAN.

3. The computing system of claim 1 wherein the SAN comprises a first network and a second network, the nFE_SAN being configured to send data from the first writeback cache to the at least one nBE_SAN over the first network and from the second writeback cache to the at least one nBE_SAN over the second network.

4. The system of claim 1 wherein the nFE_SAN is coupled to the processor through an interconnect selected from the group consisting of PCI, PCle, SBus, IBM Coherent Accelerator Processor Interface (CAPI), QuickPath Interconnect (QPI), HyperTransport (HT), and a memory channel interface.

5. A computing system of the type comprising at least one processor (CPU) coupled through at least one front-end storage controller (nFE_SAN) to a storage-area network (SAN), the SAN coupled through at least one back-end storage controller (nBE_SAN) to a plurality of storage devices, the improvement comprising:

a first nFE_SAN of the at least one nFE_SAN having a first and a second write-back cache module configured to, upon receiving a write command addressed to a data block, to receive write data from the at least one CPU, maintain a first copy of the write data in the first write-back cache module and a second copy of the write data in the second write-back cache module of data written by the at least one processor to the storage devices until the data is written to the at least one nBE_SAN, the first write-back cache module configured to receive power from a first power supply and the second write-back cache module configured to receive power from a second power supply;

the first nFE_SAN coupled to the at least one nBE_SAN through a first SAN and through a second SAN;

the nFE_SAN configured to be capable of transmitting data from the first write-back cache module to the at least one nBE_SAN over the first SAN when the first power supply is operational, and capable of transmitting data from the second write-back cache module to the at least one nBE_SAN when the second power supply is operational and the first power supply not operational; and

the nFE_SAN configured to provide a write command complete response to the at least one CPU upon receiving the write data into the first and second writeback cache;

wherein a first nBE_SAN of the at least one nBE_SAN comprises a third and a fourth writeback cache, the first nBE_SAN being configured, upon receiving the write data from the nFE_SAN, to maintain a copy of the write data in both the third and the fourth writeback cache until the write data is written to at least one storage device of the plurality of storage devices.

6. The computing system of claim 5 wherein the nFE_SAN is configured to request a write data lock from the at least one nBE_SAN for the data block upon receiving the write command, and to provide the write command complete response to the at least one CPU upon receiving the write data into the first and second writeback cache and receiving a write data lock from the at least one nBE_SAN.

7. The computing system of claim 6 wherein the SAN comprises a first network and a second network, the nFE_SAN being configured to send data from the first writeback cache to the at least one nBE_SAN over the first network and from the second writeback cache to the at least one nBE_SAN over the second network.

8. The computing system of claim 7 wherein the second network and first network are of different types.

9. The computing system of claim 7 wherein the nFE_SAN further comprises a firmware selected from the group consisting of data compression firmware and data encryption firmware.

10. The computing system of claim 9 wherein the nFE_SAN further comprises a distributed resource manager adapted to recognize write data addresses associated with a first and a second nBE_SAN, and of routing communications to the nBE_SAN associated with the write data address.

11. The computing system of claim 7 wherein the nFE_SAN further comprises a firmware selected from the group consisting of de-duplication firmware and thin-provisioning firmware.

12. A method of writing write data to at least one storage device comprising:

generating a write request in a computer processor;

passing the write request to a front-end storage controller (nFE_SAN);

copying the write data to a first and a second cache memory of the nFE_SAN;

generating a write lock request and transmitting the write lock request from the nFE_SAN over a network interconnect selected from a first and a second storage area interconnect to a back-end storage controller (nBE_SAN);

returning a write lock grant from the nBE_SAN to the nFE_SAN;

upon completing copying the write data to the first and second cache memory of the nFE_SAN and receiving the write lock grant from the nBE_SAN, the nFE_SAN providing a write complete signal to the computer processor;

copying the write data over a network interconnect selected from the first and second storage area interconnect to the nBE_SAN;

writing, by the nBE_SAN, the write data to the at least one storage device; and

writing the write data into a third and a fourth cache memory disposed within the nBE_SAN.

13. The method of claim 12 wherein, upon failure of the first cache memory of the nFE_SAN, the write data is copied from the second cache memory of the nFE_SAN to the nBE_SAN.