Reset circuit, shift register unit, and gate scanning circuit
First Claim
1. A reset circuit for compensating a reduction of a level at a first node of a circuit during a first stage without affecting levels at the first node during a second stage, comprising a reset unit circuit, a reset control unit circuit, and at least three input terminals, wherein:
- the at least three input terminals comprise a first input terminal, a second input terminal, and a third input terminal, wherein the first input terminal is coupled to the first node;
the reset unit circuit is coupled to the first input terminal, the second input terminal, and a second node, and is configured to be turned on if the second node is at a first level, so as to electrically couple the second input terminal with the first input terminal; and
the reset control unit circuit is coupled to the first input terminal, the second input terminal, the third input terminal, and the second node, and is configured to electrically couple the second input terminal with the second node if the first input terminal is at the first level, and to electrically couple the second node with the third input terminal if the second input terminal is at a second level.
1 Assignment
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Accused Products
Abstract
A reset circuit for compensating a level reduction at a first node during a first stage without affecting levels during a second stage includes a reset portion, a reset control portion, and at least three input terminals. The reset portion is coupled to the first and second input terminals, and a second node, and is configured to be turned on if the second node is at a first level, to electrically couple the second and first input terminals. The reset control portion is coupled to the first, second, and third input terminals, and the second node, and is configured to electrically couple the second input terminal with the second node if the first input terminal is at the first level, and to electrically couple the second node with the third input terminal if the second input terminal is at a second level.
3 Citations
20 Claims
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1. A reset circuit for compensating a reduction of a level at a first node of a circuit during a first stage without affecting levels at the first node during a second stage, comprising a reset unit circuit, a reset control unit circuit, and at least three input terminals, wherein:
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the at least three input terminals comprise a first input terminal, a second input terminal, and a third input terminal, wherein the first input terminal is coupled to the first node; the reset unit circuit is coupled to the first input terminal, the second input terminal, and a second node, and is configured to be turned on if the second node is at a first level, so as to electrically couple the second input terminal with the first input terminal; and the reset control unit circuit is coupled to the first input terminal, the second input terminal, the third input terminal, and the second node, and is configured to electrically couple the second input terminal with the second node if the first input terminal is at the first level, and to electrically couple the second node with the third input terminal if the second input terminal is at a second level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification