Nonvolatile memory system with retention monitor

• US 10,332,613 B1
• Filed: 05/18/2015
• Issued: 06/25/2019
• Est. Priority Date: 05/18/2015
• Status: Active Grant

• Current Assignee: Microsemi Solutions (U.S.), Inc. (Microchip Technology Incorporated)
• Original Assignee: Microsemi Solutions (U.S.), Inc. (Microchip Technology Incorporated)
• Inventors: Micheloni, Rino, Marelli, Alessia, Fryman, Robert Scott
• Primary Examiner(s): Blair, April Y
• Assistant Examiner(s): Gandhi, Dipakkumar B
• Application Number:
  US14/715,403
• Time in Patent Office: 1,499 Days
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/56016 Apparatus features
• CPC Class Codes: G11C 29/702 by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones

Abstract

A nonvolatile memory system, a nonvolatile memory controller and a method for assuring retention are disclosed. The nonvolatile memory controller includes a retention monitor that stores test characteristics corresponding to a use case and determines, each time that a read of a codeword is performed, whether the number of errors in the codeword exceed a retention threshold. If the number of errors in the codeword exceed the retention threshold, the block containing the codeword is retired. The retention monitor performs retention tests during the operation of the memory controller and adjusts the retention threshold when the results of the retention tests indicate deviation from the test characteristics corresponding to a use case.

Claims

1. A nonvolatile memory controller including a programming circuit for programming a nonvolatile memory device using an error correction code having a maximum error correction capacity, a read circuit for sending an instruction to perform a read operation to the nonvolatile memory device, a decode circuit for decoding the results of the read operation and for determining a number of errors in the read operation, memory storage for storing a threshold value, a comparison circuit for comparing the determined number of errors in the read operation to the stored threshold value and a circuit for retiring a block or page of the nonvolatile memory device when the determined number of errors exceeds the stored threshold value, a start-up circuit to initiate normal operation of the nonvolatile memory controller in response to receiving one or more of a power-on signal, a start-up signal and applied power at the nonvolatile memory controller, and a power-down circuit configured to power down the nonvolatile memory controller in response to receipt of a power-off signal at the nonvolatile memory controller, the nonvolatile memory controller comprising:

a first offline test circuit coupled to the read circuit, the decode circuit and the power-down circuit, the first offline test circuit operable to perform a first offline test by instructing the read circuit, after the power-off signal is received and prior to a subsequent powering down of the nonvolatile memory controller, to perform a first read of each of a plurality of test codewords stored on the nonvolatile memory device, the decode circuit operable to decode each of the reads of the first offline test to determine a number of errors in the performed first read of each of the test codewords, and the first offline test circuit operable to compare each determined number of errors in the first read of each test codeword to a determined number of errors in the first read of a different one of the test codewords to identify a number of errors in the first read of the plurality of test codewords having the highest number of errors at a first time;

a second offline test circuit coupled to the read circuit, the decode circuit and the start-up circuit, the second offline test circuit operable to perform a second offline test by instructing the read circuit, after receipt of one or more of the power-on signal, the start-up signal and the applied power and prior to a subsequent initiating normal operation of the nonvolatile memory controller, to perform a second read of each of the test codewords, the decode circuit operable to decode each of the second reads to determine a number of errors in the second read of each of the test codewords, and the second offline test circuit operable to compare each determined number of errors in the second read of each test codeword to a determined number of errors in the second read of a different one of the test codewords to identify a number of errors in the second read of the plurality of test codewords having the highest number of errors at a second time; and

a retention monitor circuit coupled to the first offline test circuit and to the second offline test circuit, the retention monitor circuit operable to subtract the number of errors in the test codeword having the highest number of errors at the first time from the number of errors in the test codeword having the highest number of errors at the second time to identify a delta worst value, to subtract the delta worst value from the maximum error correction capacity of the error correction code to determine a delta worst retention threshold, to compare the delta worst retention threshold to the stored threshold value and to replace the stored threshold value with the delta worst retention threshold if the delta worst retention threshold exceeds the stored threshold value.

2. The nonvolatile memory controller of claim 1 wherein the nonvolatile memory controller further comprises a Field Programmable Gate Array (FPGA).

3. A nonvolatile memory controller including a programming circuit for programming a nonvolatile memory device, a read circuit for sending an instruction to perform a read operation to the nonvolatile memory device, a decode circuit for decoding the results of the read operation and for determining a number of errors in the read operation, memory storage for storing a threshold value, a comparison circuit for comparing the determined number of errors in the read operation to the stored threshold value and a circuit for retiring a block or page of the nonvolatile memory device when the determined number of errors exceeds the stored threshold value, a start-up circuit configured to initiate normal operation of the nonvolatile memory controller in response to receiving at the nonvolatile memory controller one or more of a power-on signal, a start-up signal and applied power, and a power-down circuit configured to power down the nonvolatile memory controller in response to receiving a power-off signal at the nonvolatile memory controller, the nonvolatile memory controller comprising:

an online test circuit configured to periodically perform an online retention test by reading a first codeword stored in the nonvolatile memory device and determine a number of errors in the first codeword at a first time, repeating the reading the first codeword and the determining the number of errors in the first codeword to determine a number of errors in the first codeword at a second time, determine a marginal error rate by subtracting the determined number of errors in the first codeword at the first time from the determined number of errors in the first codeword at the second time, determine the temperature of the memory controller, determine an acceleration factor corresponding to the determined temperature, and update the stored threshold value if the determined marginal error rate multiplied by the acceleration factor exceeds a characterized marginal error rate corresponding to a use case; and

a first offline test circuit coupled to the read circuit and the decode circuit and the power-down circuit, the first offline test circuit operable to perform a first offline test by instructing the read circuit, after the power-off signal is received and prior to a subsequent powering down the nonvolatile memory controller, to perform a first read of each of a plurality of test codewords stored on the nonvolatile memory device, the decode circuit operable to decode each of the reads in the first offline test to determine a number of errors in a first read of each of the test codewords, and the first offline test circuit further configured to compare each determined number of errors in the first read of the test codeword to a determined number of errors in the first read of a different one of the test codewords to identify a number of errors in the test codeword having the highest number of errors at a third time;

a second offline test circuit coupled to the read circuit, the decode circuit and the start-up circuit, the second offline test circuit operable to perform a second offline test by instructing the read circuit, after the receiving at the nonvolatile memory controller one or more of a power-on signal, a start-up signal and applied power and prior to a subsequent initiating normal operation of the nonvolatile memory controller, to perform a second read of each of the test codewords, the decode circuit operable to decode each of the reads in the second offline test to determine a number of errors in the second read of each of the test codewords, and the second offline test circuit operable to compare each determined number of errors in the second read of each test codeword to a determined number of errors in the second read of a different one of the test codewords to identify a number of errors in the test codeword having the highest number of errors at a fourth time; and

a timing circuit configured to determine offline retention time, wherein the offline retention time is the duration of a time interval that starts after the power-off signal is received and prior to the subsequent powering down the nonvolatile memory controller, and stops after the receiving at the nonvolatile memory controller one or more of a power-on signal, a start-up signal and applied power, and prior to the subsequent initiating normal operation of the nonvolatile memory controller; and

a retention monitor circuit coupled to the first offline test circuit, the second offline test circuit and the timing circuit, the retention monitor circuit configured to subtract the number of errors in the test codeword having the highest number of errors at the third time from the number of errors in the test codeword having the highest number of errors at the fourth time to determine a delta worst value, to compare the delta worst value to an offline test characteristics corresponding to the use case, to compare the determined offline retention time to a time value corresponding to the use case, and to replace the stored threshold value with an adjusted threshold value when the comparison indicates that the delta worst value exceeds the offline test characteristic corresponding to the use case and the determined offline retention time does not exceed the time value corresponding to the use case.

4. The nonvolatile memory controller of claim 3 wherein the test codewords comprise a logical block of the nonvolatile memory device.

5. The nonvolatile memory controller of claim 3 wherein the retention monitor circuit is configured to calculate the adjusted threshold value by multiplying the stored threshold value by a correction factor.

6. The nonvolatile memory controller of claim 3 wherein the nonvolatile memory controller further comprises a Field Programmable Gate Array (FPGA).

7. A nonvolatile memory controller including a programming circuit for programming a nonvolatile memory device, a read circuit for sending an instruction to perform a read operation to the nonvolatile memory device, a decode circuit for decoding the results of the read operation and for determining a number of errors in the read operation, a comparison circuit for comparing the determined number of errors in the read operation to a stored threshold value and a circuit for retiring a block or page of the nonvolatile memory device when the determined number of errors exceeds the stored threshold value, a start-up circuit configured to initiate normal operation of the nonvolatile memory controller in response to receiving one or more of a power-on signal, a start-up signal and applied power at the nonvolatile memory controller and a power-down circuit configured to enter a low-power mode in response to receiving a power-off signal at the nonvolatile memory controller, the nonvolatile memory controller comprising:

a first offline test circuit coupled to the read circuit, the decode circuit and the power-down circuit, the first offline test circuit operable to perform a first offline test by instructing the read circuit, after the power-off signal is received and prior to the entering the low-power mode, to perform a first read of each of a plurality of test codewords stored on the nonvolatile memory device, the decode circuit operable to decode each of the reads to determine a number of errors in a first read of each of the test codewords, and the first offline test circuit further configured to compare each determined number of errors in the first read of the test codeword to a determined number of errors in the first read of a different one of the test codewords to identify a number of errors in the test codeword having the highest number of errors at a first time; and

a second offline test circuit coupled to the read circuit, the decode circuit and the start-up circuit, the second offline test circuit operable to perform a second offline test by instructing the read circuit, after the receiving one or more of a power-on signal, a start-up signal and applied power and prior to a subsequent initiating normal operation of the nonvolatile memory controller, to perform a second read of each of the test codewords, the decode circuit operable to decode each of the reads in the second offline test to determine a number of errors in a second read of each of the test codewords, and the second offline test circuit operable to compare each determined number of errors in the second read of each test codeword to a determined number of errors in the second read of a different one of the test codewords to identify a number of errors in the test codeword having the highest number of errors at a second time;

a timing circuit for determining offline retention time, wherein the timing circuit includes a timer that is started after the power-off signal is received and prior to the entering a low-power mode and stopped after the receiving one or more of a power-on signal, a start-up signal and applied power, and prior to the subsequent initiating normal operation of the nonvolatile memory controller; and

a retention monitor circuit coupled to one or more pins, the timing circuit, the first offline test circuit and the second offline test circuit, the retention monitor circuit operable to compare the determined offline retention time and the results of the first and second offline tests to the corresponding offline test characteristics corresponding to a use case to determine whether the results of the first and second offline tests deviate from the offline test characteristics corresponding to the use case and to replace the stored threshold value with an adjusted threshold value when the comparison indicates that the results of the first and second offline tests deviate from the offline test characteristics corresponding to the use case.

8. The nonvolatile memory controller of claim 7 wherein the retention monitor circuit is configured to subtract the number of errors in the test codeword having the highest number of errors at the first time from the number of errors in the test codeword having the highest number of errors at the second time to identify a delta worst value, and is further configured to subtract the delta worst value from the maximum error correction capacity of an error correction code to determine a delta worst retention threshold, to compare the delta worst retention threshold to the stored threshold and to replace the stored threshold value with the delta worst retention threshold if the delta worst retention threshold exceeds the stored threshold value.

9. The nonvolatile memory controller of claim 7 further comprising an online test circuit configured to periodically perform an online retention test by reading a first codeword stored in the nonvolatile memory device and determine a number of errors in the first codeword at a third time, repeating the reading the first codeword and the determining the number of errors in the first codeword to determine a number of errors in the first codeword at a fourth time, determine a marginal error rate by subtracting the determined number of errors in the first codeword at the third time from the determined number of errors in the first codeword at the fourth time, determine the temperature of the memory controller, determine an acceleration factor corresponding to the determined temperature, and update the threshold if the determined marginal error rate multiplied by the acceleration factor exceeds a characterized marginal error rate corresponding to the use case.

10. The nonvolatile memory controller of claim 7 wherein the nonvolatile memory controller further comprises a Field Programmable Gate Array (FPGA).