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Nonvolatile memory system with retention monitor

  • US 10,332,613 B1
  • Filed: 05/18/2015
  • Issued: 06/25/2019
  • Est. Priority Date: 05/18/2015
  • Status: Active Grant
First Claim
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1. A nonvolatile memory controller including a programming circuit for programming a nonvolatile memory device using an error correction code having a maximum error correction capacity, a read circuit for sending an instruction to perform a read operation to the nonvolatile memory device, a decode circuit for decoding the results of the read operation and for determining a number of errors in the read operation, memory storage for storing a threshold value, a comparison circuit for comparing the determined number of errors in the read operation to the stored threshold value and a circuit for retiring a block or page of the nonvolatile memory device when the determined number of errors exceeds the stored threshold value, a start-up circuit to initiate normal operation of the nonvolatile memory controller in response to receiving one or more of a power-on signal, a start-up signal and applied power at the nonvolatile memory controller, and a power-down circuit configured to power down the nonvolatile memory controller in response to receipt of a power-off signal at the nonvolatile memory controller, the nonvolatile memory controller comprising:

  • a first offline test circuit coupled to the read circuit, the decode circuit and the power-down circuit, the first offline test circuit operable to perform a first offline test by instructing the read circuit, after the power-off signal is received and prior to a subsequent powering down of the nonvolatile memory controller, to perform a first read of each of a plurality of test codewords stored on the nonvolatile memory device, the decode circuit operable to decode each of the reads of the first offline test to determine a number of errors in the performed first read of each of the test codewords, and the first offline test circuit operable to compare each determined number of errors in the first read of each test codeword to a determined number of errors in the first read of a different one of the test codewords to identify a number of errors in the first read of the plurality of test codewords having the highest number of errors at a first time;

    a second offline test circuit coupled to the read circuit, the decode circuit and the start-up circuit, the second offline test circuit operable to perform a second offline test by instructing the read circuit, after receipt of one or more of the power-on signal, the start-up signal and the applied power and prior to a subsequent initiating normal operation of the nonvolatile memory controller, to perform a second read of each of the test codewords, the decode circuit operable to decode each of the second reads to determine a number of errors in the second read of each of the test codewords, and the second offline test circuit operable to compare each determined number of errors in the second read of each test codeword to a determined number of errors in the second read of a different one of the test codewords to identify a number of errors in the second read of the plurality of test codewords having the highest number of errors at a second time; and

    a retention monitor circuit coupled to the first offline test circuit and to the second offline test circuit, the retention monitor circuit operable to subtract the number of errors in the test codeword having the highest number of errors at the first time from the number of errors in the test codeword having the highest number of errors at the second time to identify a delta worst value, to subtract the delta worst value from the maximum error correction capacity of the error correction code to determine a delta worst retention threshold, to compare the delta worst retention threshold to the stored threshold value and to replace the stored threshold value with the delta worst retention threshold if the delta worst retention threshold exceeds the stored threshold value.

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