Post UV cure for gapfill improvement

• US 10,332,746 B1
• Filed: 03/14/2018
• Issued: 06/25/2019
• Est. Priority Date: 03/14/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, De-Wei, Chen, Chien-Hao, Peng, Chih-Tang, Chen, Jei Ming, Wang, Shu-Yi
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US15/920,753
• Time in Patent Office: 468 Days
• CPC Class Codes: H01L 21/02348 treatment by exposure to UV light
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.

Claims

1. A method for semiconductor processing, the method comprising:

performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate;

performing an etch process to remove a portion of the conformal film;

repeating the first deposition process and the etch process to fill the feature with the conformal film; and

exposing the conformal film to ultraviolet light.

2. The method of claim 1, wherein the conformal film is amorphous silicon.

3. The method of claim 1, wherein the conformal film is exposed to the ultraviolet light by an H type bulb.

4. The method of claim 1, further comprising:

heating the conformal film before exposing the conformal film to the ultraviolet light.

5. The method of claim 4, wherein the conformal film is heated at an ambient temperature in a range from 250 degrees Celsius to 450 degrees Celsius.

6. The method of claim 1, wherein the first deposition process and the etch process are repeated until lateral growth fronts of the conformal film grown from the respective sidewall surfaces of the feature merge together.

7. The method of claim 1, wherein after the repeating the first deposition process and the etch process and before the exposing the conformal film to the ultraviolet light, the conformal film includes a first number of voids or seams, and wherein after the exposing the conformal film to the ultraviolet light, the conformal film includes a second number of voids or seams, the second number being smaller than the first number.

8. The method of claim 1, further comprising:

after exposing the conformal film, performing a second deposition process to deposit the film to a target thickness above the feature.

9. A method for semiconductor processing, the method comprising:

forming fins on a substrate, sidewalls of the fins and a bottom surface between the sidewalls of the fins defining a trench therebetween;

forming a gate layer in the trench and over the fins, forming the gate layer comprising;

depositing at least a portion of the gate layer in the trench by performing a cyclic deposition-etch process, the at least the portion of the gate layer merging by lateral growth from the sidewalls of the fins;

exposing the at least the portion of the gate layer to ultraviolet light; and

after forming the gate layer, patterning the gate layer to form a gate structure over the fins.

10. The method of claim 9, wherein the gate layer comprises amorphous silicon.

11. The method of claim 9, wherein exposing the at least the portion of the gate layer comprises exposing the at least the portion of the gate layer to ultraviolet light by an H type bulb.

12. The method of claim 9, wherein exposing the at least the portion of the gate layer to the ultraviolet light further comprises heating the at least the portion of the gate layer.

13. The method of claim 12, wherein the gate layer is heated in an ambient temperature in a range from 250 degrees Celsius to 450 degrees Celsius.

14. The method of claim 9, wherein the cyclic deposition-etch process is performed until the at least the portion of the gate layer has a thickness that is equal to or greater than half a distance between the sidewalls of the fins.

15. The method of claim 9, wherein after the cyclic deposition-etch process is performed, the gate layer includes a first number of seams or voids, and wherein after exposing the at least the portion of the gate layer to the ultraviolet light, the gate layer includes a second number of voids or seams smaller than the first number.

16. The method of claim 9, wherein forming the gate layer further comprises:

after exposing the at least the portion of the gate layer to the ultraviolet light, depositing a remaining portion of the gate layer.

17. A method for semiconductor processing, the method comprising:

forming fins on a substrate, sidewalls of the fins and a bottom surface defining a trench therebetween;

forming a dummy gate structure over the fins, wherein forming the dummy gate structure comprises;

performing a cyclic deposition-etch process to deposit a first film over the fins, the first film comprising a portion of a dummy gate layer;

performing an ultraviolet (UV) curing process to expose the first film to ultraviolet light; and

performing a deposition process to deposit a second film over the first film, the second film comprising a remaining portion of the dummy gate layer;

removing the dummy gate structure to form an opening; and

forming a replacement gate structure over the fins in the opening.

18. The method of claim 17 further comprising forming a spacer structure on a sidewall of the dummy gate structure;

wherein;

before the spacer structure is formed, the dummy gate layer comprises amorphous silicon; and

after the spacer structure is formed, the dummy gate layer comprises polycrystalline silicon.

19. The method of claim 17, wherein the UV curing process exposes the first film to ultraviolet light by an H type bulb.

20. The method of claim 17, wherein after the cyclic deposition-etch process the first film includes a first number of voids or seams, and wherein after performing the UV curing process the first film includes a second number of voids or seams smaller than the first number.