Schemes for forming barrier layers for copper in interconnect structures

• US 10,332,838 B2
• Filed: 01/02/2018
• Issued: 06/25/2019
• Est. Priority Date: 11/21/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chen, Hai-Ching, Bao, Tien-I
• Primary Examiner(s): Sarkar, Asok K
• Application Number:
  US15/860,014
• Publication Number:
  US 20180130752A1
• Time in Patent Office: 539 Days
• Field of Search: None
• CPC Class Codes: H01L 21/322 to modify their internal properties, e.g. to produce internal imperfections
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Claims

1. A semiconductor device comprising:

a conductive material embedded within a dielectric layer, the conductive material comprising a first element;

a first barrier layer lining sidewalls and a bottom surface of the conductive material, the first barrier layer comprising a second element different from the first element; and

a capping layer over the conductive material and the first barrier layer but not extending over the dielectric layer, the capping layer comprising;

a first material in physical contact with the conductive material, wherein the first material comprises the first element and a third element, the third element being different from the first element and the second element; and

a second material in physical contact with the first barrier layer, wherein the second material comprises the second element and the third element.

2. The semiconductor device of claim 1, wherein the third element is silicon.

3. The semiconductor device of claim 1, wherein the capping layer extends into a recess between the conductive material and the dielectric layer.

4. The semiconductor device of claim 3, wherein the recess has a first depth of greater than about 50 Å

.

5. The semiconductor device of claim 3, wherein the recess has a first depth of greater than about 5% of a thickness of the conductive material.

6. The semiconductor device of claim 1, wherein the second element is cobalt.

7. The semiconductor device of claim 1, wherein a thickness of the first material is different from a thickness of the second material.

8. A semiconductor device comprising:

a conductive material extending into a dielectric layer, the conductive material comprising a first element;

a first barrier layer lining sidewalls of the conductive material, the first barrier layer comprising a second element different from the first element; and

a second barrier layer over the conductive material and the first barrier layer, the second barrier layer comprising;

a first region in physical contact with the conductive material, the first region comprising a silicide of the first element, the first region having a first thickness; and

a second region in physical contact with the first barrier layer, the second region comprising a silicide of the second element, the second region having a second thickness different from the first thickness.

9. The semiconductor device of claim 8, wherein at least a portion of the second barrier layer extends below a topmost surface of the conductive material.

10. The semiconductor device of claim 8, wherein at least a portion of the second barrier layer extends below a topmost surface of the dielectric layer.

11. The semiconductor device of claim 8, wherein the first thickness is between about 5 Å

and about 100 Å

.

12. The semiconductor device of claim 8, wherein the second thickness is between about 5 Å

and about 100 Å

.

13. The semiconductor device of claim 8, wherein a topmost surface of the conductive material is substantially level with a topmost surface of the dielectric layer.

14. The semiconductor device of claim 8, wherein portions of the second region of the second barrier layer extend along the sidewalls of the conductive material.

15. A semiconductor device comprising:

a dielectric layer extending along a sidewall of a conductive material, the conductive material comprising a first element;

a first barrier layer between the sidewall of the conductive material and the dielectric layer, the first barrier layer comprising a second element different from the first element; and

a second barrier layer over the conductive material and the first barrier layer, the second barrier layer comprising;

a first region extending along a topmost surface of the conductive material, wherein the first region comprises the first element and a third element, the third element being different from the first element and the second element; and

a second region extending along a topmost surface of the first barrier layer, wherein the second region comprises the second element and the third element.

16. The semiconductor device of claim 15, wherein the second region of the second barrier layer extends along the sidewall of the conductive material.

17. The semiconductor device of claim 15, wherein an interface between the first barrier layer and the second barrier layer is lower than the topmost surface of the conductive material.

18. The semiconductor device of claim 15, wherein the second barrier layer is separated from the dielectric layer.

19. The semiconductor device of claim 15, wherein a thickness of the first barrier layer is greater than a thickness of the second barrier layer.

20. The semiconductor device of claim 15, wherein a portion of the topmost surface of the first barrier layer is not covered by the second barrier layer.