Anchoring structure of fine pitch bva

• US 10,332,854 B2
• Filed: 10/24/2016
• Issued: 06/25/2019
• Est. Priority Date: 10/23/2015
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Katkar, Rajesh, Guevara, Gabriel Z., Li, Xuan, Uzoh, Cyprian Emeka, Gao, Guilian, Wang, Liang
• Primary Examiner(s): Stark, Jarrett J
• Application Number:
  US15/332,533
• Publication Number:
  US 20170117243A1
• Time in Patent Office: 974 Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/1182 Applying permanent coating, e.g. in-situ coating
• CPC Class Codes: H01L 2224/11822 by dipping, e.g. in a solder bath
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/1329 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/133 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13566 Both on and outside the bonding interface of the bump connector
• CPC Class Codes: H01L 2224/1357 Single coating layer
• CPC Class Codes: H01L 2224/13639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16111 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 : Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/85355 : having an external coating, e.g. protective bond-through coating
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1082 : for improving alignment between containers, e.g. interlocking features
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/20751 : larger or equal to 10 microns less than 20 microns
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/20754 : larger or equal to 40 microns less than 50 microns
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns

Abstract

A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.

Claims

1. A microelectronic package, comprising:

a substrate having a first surface and a second surface opposite therefrom and having first conductive elements at the first surface;

a plurality of wire bonds each having a base electrically connected to a corresponding one of the first conductive elements, a tip remote from the base corresponding thereto, and an edge surface extending between the tip and the base corresponding thereto;

an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having defined therein a plurality of recesses extending from the major surface in a direction toward the first surface of the substrate;

the plurality of recesses in the encapsulation layer each including a plurality of extended portions extending into the encapsulation layer and spaced apart from one another at an interval;

tips of the plurality of wire bonds being disposed within the plurality of recesses;

an electrically conductive barrier layer overlying at least a portion of an inner surface of the encapsulation defined by the plurality of recesses including the plurality of extended portions for partially filling thereof and overlying the tips of the plurality of wire bonds, wherein the electrically conductive barrier layer provides barrier and adhesion properties in a single layer with only the single layer between the encapsulation and the plurality of wire bonds; and

joining units at least partially extending within the plurality of recesses, the joining units respectively filling remaining volumes of the plurality of recesses for electrical conductivity between the plurality of wire bonds and the second conductive elements, wherein the joining units are interconnected to the at least the portion of the inner surface of the plurality of recesses and the tips of the wire bonds responsive to intermetallic compounds formed between the joining units and the electrically conductive barrier layer for electrical conductivity between the joining units and the tips.

2. The microelectronic package of claim 1, wherein a portion of the edge surface-adjacent to the tip corresponding thereto is disposed within a recess of the plurality of recesses with the electrically conductive barrier layer overlying the portion of the edge surface.

3. The microelectronic package of claim 1, wherein the plurality of recesses of the encapsulation defining the inner surface provide a contour with the extended portions thereof penetrating into the encapsulation layer at a 90 degree angle relative to a portion of the contour of the inner surface closer to the major surface.

4. The microelectronic package of claim 1, wherein the tips of the plurality of wire bonds are respectively disposed within the plurality of recesses except for at least two tips thereof being disposed within a same one of the plurality of recesses.

5. The microelectronic package of claim 4, wherein the electrically conductive barrier layer overlies the at least two tips for electrical conductivity therebetween.

6. The microelectronic package of claim 1, further comprising a microelectronic element joined to the first surface of the substrate, the microelectronic element having a top surface facing away from the first surface of the substrate, wherein the major surface of the encapsulation overlies a top surface of the microelectronic element.

7. A microelectronic assembly, comprising:

the microelectronic package of claim 1, wherein the microelectronic package is a first microelectronic package having a first substrate and first conductive elements at the first surface thereof; and

a second microelectronic package having a second substrate and second conductive elements at a surface thereof.