Multi-layer structure and a method for manufacturing the same and a corresponding contact structure

• US 10,332,903 B2
• Filed: 12/19/2016
• Issued: 06/25/2019
• Est. Priority Date: 12/19/2016
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Shih-Hung
• Primary Examiner(s): Karimy, Timor
• Application Number:
  US15/382,969
• Publication Number:
  US 20180174955A1
• Time in Patent Office: 918 Days
• Field of Search: 257751
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A method for manufacturing a multi-layer structure is provided. The method includes following steps. First, a stack of alternate conductive layers and insulating layers is formed on a substrate, and the stack includes a multi-layer area and a contact area adjacent to the multi-layer area. Next, a plurality of first openings are formed in the contact area. Then, a conductive connecting structure is formed on the stack and into the first openings. Thereafter, the stack is patterned. The conductive connecting structure continuously extends on the contact area and into the first openings to maintain an electrical connection among the conductive layers while the stack is patterned.

Claims

1. A multi-layer structure, comprising:

a silicon substrate;

a stack of alternate conductive layers and insulating layers, wherein the silicon substrate comprises a stack area corresponding to the stack and an extension area adjacent to the stack area; and

a plurality of conductive connecting structures disposed in the extension area, wherein the conductive connecting structures extend from a top surface of the silicon substrate into the silicon substrate, and the conductive connecting structures have different depths.

2. The multi-layer structure according to claim 1, wherein each of the conductive connecting layers in the extension area has a depth lager than 1000 angstrom.

3. The multi-layer structure according to claim 1, further comprising:

a trench disposed in the silicon substrate, wherein the stack is formed in the trench.

4. The multi-layer structure according to claim 1, wherein the stack comprises a multi-layer area and a contact area, the conductive layers in the contact area and the silicon substrate in the extension area have a first staircase structure and a second staircase structure respectively.

5. The multi-layer structure according to claim 1, further comprising:

a plurality of contact structures vertically extending in the contact area, wherein the contact structures and the conductive connecting structures have a same material.

6. The multi-layer structure according to claim 1, wherein a top surface of the stack is aligned with the top surface of the silicon substrate.