Control circuitry for 1D optical metasurfaces

• US 10,332,923 B2
• Filed: 11/28/2017
• Issued: 06/25/2019
• Est. Priority Date: 02/22/2017
• Status: Active Grant

• Current Assignee: Elwha LLC (Intellectual Ventures LLC)
• Original Assignee: Elwha LLC (Intellectual Ventures LLC)
• Inventors: Josberger, Erik E., Akselrod, Gleb M., Weidman, Mark C.
• Primary Examiner(s): Booth, Richard A
• Application Number:
  US15/824,189
• Publication Number:
  US 20180239304A1
• Time in Patent Office: 574 Days
• CPC Class Codes: B29D 11/00326 having particular surface properties, e.g. a micropattern
• CPC Class Codes: B29D 11/00346 having nanosize structures or features, e.g. fillers
• CPC Class Codes: B29D 11/0074 Production of other optical elements not provided for in B29D11/00009- B29D11/0073
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: G01S 17/10 using transmission of interrupted, pulse-modulated waves determination of distance by phase measurements G01S17/32
• CPC Class Codes: G01S 17/42 Simultaneous measurement of distance and other co-ordinates indirect measurement G01S17/46
• CPC Class Codes: G01S 17/89 for mapping or imaging
• CPC Class Codes: G01S 7/4813 Housing arrangements
• CPC Class Codes: G01S 7/4817 relating to scanning
• CPC Class Codes: G02B 5/1809 with pitch less than or comparable to the wavelength
• CPC Class Codes: G02B 6/1226 involving surface plasmon interaction
• CPC Class Codes: G02F 1/0107 Gaskets, spacers or sealing of cells; Filling and closing of cells
• CPC Class Codes: G02F 1/13342 Holographic polymer dispersed liquid crystals
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/1341 Filling or closing of cells
• CPC Class Codes: G02F 1/292 by controlled diffraction or phased-array beam steering controlled diffraction for optical switching G02F1/31
• CPC Class Codes: G02F 2202/103 a-Si
• CPC Class Codes: G02F 2202/30 Metamaterials
• CPC Class Codes: G02F 2202/36 Micro- or nanomaterials
• CPC Class Codes: G03F 7/2041 in the presence of a fluid, e.g. immersion; using fluid cooling means
• CPC Class Codes: G03F 7/2059 : using a scanning corpuscular radiation beam, e.g. an electron beam
• CPC Class Codes: G03H 1/00 : Holographic processes or apparatus using light, infrared or ultraviolet waves for obtaining holograms or for obtaining an image from them; Details peculiar thereto
• CPC Class Codes: G03H 1/0244 : Surface relief holograms replicating hologram without interference recording G03H1/0276
• CPC Class Codes: G03H 1/0443 : Digital holography, i.e. recording holograms with digital recording means holobject computation G03H1/0866
• CPC Class Codes: G03H 2240/13 : Amplitude and phase complex modulation
• CPC Class Codes: H01J 2237/334 : Etching
• CPC Class Codes: H01J 37/3174 : Particle-beam lithography, e.g. electron beam lithography
• CPC Class Codes: H01J 37/32816 : Pressure
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 27/14625 : Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14643 : Photodiode arrays; MOS imagers
• CPC Class Codes: H01Q 1/38 : formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H01Q 15/002 : said selective devices being reconfigurable or tunable, e.g. using switches or diodes
• CPC Class Codes: H01Q 15/0066 : said selective devices being reconfigurable, tunable or controllable, e.g. using switches
• CPC Class Codes: H01Q 15/02 : Refracting or diffracting devices, e.g. lens, prism
• CPC Class Codes: H01Q 15/148 : with means for varying the reflecting properties H01Q15/147 takes precedence
• CPC Class Codes: H01Q 3/44 : varying the electric or magnetic characteristics of reflecting, refracting, or diffracting devices associated with the radiating element
• CPC Class Codes: H04N 23/54 : Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A hologram system may include a hologram chip comprising a wafer substrate having a first plurality of conductive pads on a hologram surface region connected to a second plurality of conductive pads on an interconnect surface region. The hologram chip may also include an array of sub-wavelength hologram elements integrated with a refractive index tunable core material on the hologram region of the wafer substrate. The hologram system may also include a control circuit chip having a third plurality of conductive pads connected to the second plurality of conductive pads on the interconnect region of the wafer substrate. The interconnect region is on the same side of the wafer substrate as the hologram region. The first plurality of conductive pads is directly connected to the array of sub-wavelength hologram elements.

Claims

1. A hologram system comprising:

a hologram chip comprising a wafer substrate having a first plurality of conductive pads on a hologram surface region connected to a second plurality of conductive pads on an interconnect surface region and an array of sub-wavelength hologram elements integrated with a refractive index tunable core material on the hologram region of the wafer substrate; and

a control circuit chip having a third plurality of conductive pads connected to the second plurality of conductive pads on the interconnect region of the wafer substrate,

wherein the interconnect region is on the same side of the wafer substrate as the hologram region, and

wherein the first plurality of conductive pads are directly connected to the array of sub-wavelength hologram elements.

2. The hologram system of claim 1, wherein the array of sub-wavelength hologram elements is a plurality of nano-walls arranged in a one-dimensional array, and the plurality of nano-walls is respectively coupled to the first plurality of conductive pads.

3. The hologram system of claim 1, wherein the first plurality of conductive pads is connected to the second plurality of conductive pads by an interconnecting wire bus.

4. The hologram system of claim 1, wherein the second plurality of conductive pads is connected to the third plurality of conductive pads via solder bumps.

5. The hologram system of claim 1, wherein the chip is a CMOS chip.

6. The hologram system of claim 1, wherein the wafer substrate comprises silicon.

7. The hologram system of claim 1, wherein each of the first, second, and third plurality of conductive pads comprises a respective first, second, and third plurality of sub-group of conductive pads.

8. The hologram system of claim 6, wherein the first plurality of sub-group of conductive pads are electrically connected to the second plurality of sub-group of conductive pads.

9. The hologram system of claim 7, wherein the second plurality of sub-group of conductive pads are electrically connected to the third plurality of sub-group of conductive pads.

11. The hologram system of claim 9, wherein the one or more respective wafer substrates comprise silicon.

12. The hologram system of claim 9, wherein the one or more arrays of sub-wavelength hologram elements are aligned with each other.

13. The hologram system of claim 9, wherein the one or more respective wafer substrates are in a square shape or a rectangular shape.

14. The hologram system of claim 13, wherein the control circuit chip is a CMOS chip.

15. The hologram system of claim 9, wherein the interposer comprises a first plurality of conductive pads in a hologram region and a second plurality of conductive pads in an interconnect region, wherein the first plurality of conductive pads are connected to the second plurality of pads in the interposer, and wherein the first plurality of conductive pads comprising one or more subsets of conductive pads.

16. The hologram system of claim 14, wherein each of the one or more hologram chips having a third plurality of conductive pads connected between the plurality of silicon through vias and the respective subset of the first plurality of conductive pads in the hologram region, such that one or more arrays of sub-wavelength hologram elements are electrically coupled to the plurality of conductive pads on the hologram region of the interposer.

17. The hologram system of claim 14, wherein the second plurality of conductive pads on the interposer is connected to a fourth plurality of pads of the control circuit chip.

18. The hologram system of claim 14, wherein the first plurality of conductive pads and second plurality of conductive pads are near the edge of the respective region of the interposer.

19. The hologram system of claim 9, wherein the one or more arrays of sub-wavelength hologram elements comprise a plurality of nano-walls arranged in a one-dimensional array, and the plurality of nano-walls is respectively coupled to the first plurality of conductive pads.

20. The hologram system of claim 9, wherein the first plurality of conductive pads is connected to the second plurality of conductive pads by an interconnecting wire bus.

21. The hologram system of claim 9, wherein the second plurality of conductive pads is connected to the fourth plurality of conductive pads via solder bumps, wherein the one or more subsets of first plurality of conductive pads are connected to the respective third plurality of conductive pads via solder bumps.

10. A hologram system comprising:

one or more hologram chips, each of the one or more hologram chips comprising an array of sub-wavelength hologram elements integrated with a refractive index tunable core material on a wafer substrate and a plurality of through-vias in the respective wafer substrates;

an interposer positioned under the one or more hologram chips and electrically coupled to the one or more hologram chips; and

a control circuit chip disposed on the top of the interposer, the control circuit chip electrically connected to the one or more arrays of sub-wavelength hologram elements through the respective plurality of through-vias in each of the one or more respective wafer substrates for the one or more hologram chips,

wherein each of the one or more respective wafer substrates are positioned between the interposer and the one or more arrays of sub-wavelength holograph elements.