Resistive memory device

• US 10,333,065 B2
• Filed: 08/07/2017
• Issued: 06/25/2019
• Est. Priority Date: 07/25/2014
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Tan, Shyue Seng, Toh, Eng Huat, Tran, Xuan Anh, Sun, Yuan, Quek, Elgin Kiok Boone
• Primary Examiner(s): Spalla, David C
• Application Number:
  US15/669,990
• Publication Number:
  US 20170358744A1
• Time in Patent Office: 687 Days
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/821 Device geometry
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A non-volatile memory device and a manufacturing method thereof are provided. The memory device includes a substrate, a lower cell dielectric layer with gate conductors and a body unit conductor disposed on the lower cell dielectric layer and gates. Memory element conductors are disposed on the body unit and lower cell dielectric layer. An upper cell dielectric layer may be on the substrate and over the lower cell dielectric layer, body unit conductor and memory element conductors. The upper cell dielectric layer isolates the memory element conductors.

Claims

1. A device comprising:

a substrate prepared with a lower cell dielectric layer with first type conductors disposed in a first direction, wherein the first type conductors comprise gate conductors, wherein the first type conductors are elongated first type conductors and separated by the lower cell dielectric layer, and wherein at least a portion of the elongated first type conductors are formed in the lower cell dielectric layer;

a body unit conductor disposed on the lower cell dielectric layer and first type conductors, wherein the body unit conductor is disposed in and extends along a second direction orthogonal to the first direction and traverses the first type conductors;

second type conductors disposed on the body unit conductor, wherein the second type conductors are elongated second type conductors disposed in and extends along the same first direction over the first type conductors; and

an upper cell dielectric layer on the substrate over the lower cell dielectric layer, body unit conductor and second type conductors.

2. The device of claim 1 wherein the first type conductors have a planar surface with the lower cell dielectric layer.

3. The device of claim 1 wherein:

the first type conductors have a top surface disposed over a top surface of the lower cell dielectric layer, creating first type conductor mesas;

the body unit conductor is disposed on the first type conductor mesas, creating body mesas; and

the second type conductors are disposed on the body mesas.

4. The device of claim 1 wherein:

the first type conductors have a top surface disposed below a top surface of the lower cell dielectric layer, creating first type conductor recesses;

the body unit conductor is disposed on the lower cell dielectric layer and lines the first type conductor recesses, creating body recesses; and

the second type element conductors are disposed in the body recesses.

5. The device of claim 1 wherein the second type conductors comprise memory element conductors.

6. The device of claim 5 wherein the memory element conductors comprise resistive memory element conductors.

7. The device of claim 6 wherein the resistive memory element conductors comprise phase change memory element conductors.

8. The device of claim 1 wherein the upper cell dielectric layer isolates the second type conductors from each other.

9. The device of claim 1 wherein the body unit conductor comprises:

a gate dielectric layer; and

a body layer to serve as bodies of transistors of a column of memory cells.

10. The device of claim 9 wherein the gate dielectric layer serves as a common gate dielectric layer of columns of memory cells.

11. The device of claim 9 wherein the body layer comprises silicon.

12. The device of claim 9 wherein the body layer is arranged in a NAND configuration.

13. The device of claim 1 wherein

the second type conductors comprise memory element conductors;

the body unit conductor comprises a transistor body layer and a gate dielectric layer, wherein first and second source/drain (S/D) regions and channel regions of cell select transistors are disposed in the transistor body layer; and

each of the memory element conductors comprises first and second storage terminals, wherein the first S/D region of a cell select transistor is coupled to and in direct contact with the first storage terminal while the second S/D region of the cell select transistor is coupled to and in direct contact with the second storage terminal of the memory element conductor.

14. The device of claim 13 wherein

the gate conductor and S/D regions correspond to a cell select transistor of a memory cell;

and

the memory element type conductor corresponds to a storage unit of a memory cell.

15. A device comprising:

a substrate prepared with a lower cell dielectric layer with first type conductors disposed in a first direction, wherein the first type conductors comprise gate conductors, wherein the first type conductors are separated by the lower cell dielectric layer;

a body unit conductor disposed on the lower cell dielectric layer and first type conductors, wherein the body unit conductor is disposed in and extends along a second direction orthogonal to the first direction and traverses the first type conductors;

second type conductors disposed on the body unit conductor, wherein the second type conductors comprise memory element conductors, wherein the second type conductors are disposed in and extend along a direction which is parallel to the first direction over the first type conductors; and

an upper cell dielectric layer on the substrate over the lower cell dielectric layer, body unit conductor and second type conductors.

16. The device of claim 15 wherein:

the first type conductors have a top surface disposed over a top surface of the lower cell dielectric layer, creating first type conductor mesas;

the body unit conductor is disposed on the first type conductor mesas, creating body mesas; and

the second type conductors are disposed on the body mesas.

17. The device of claim 16 wherein:

the first type conductors have a top surface disposed below a top surface of the lower cell dielectric layer, creating first type conductor recesses;

the body unit conductor is disposed on the lower cell dielectric layer and lines the first type conductor recesses, creating body recesses; and

the second type conductors are disposed in the body recesses.

18. The device of claim 15 wherein the body unit conductor comprises:

a gate dielectric layer, wherein the gate dielectric layer serves as a common gate dielectric layer of columns of memory cell; and

a body layer to serve as bodies of transistors of a column of memory cells.