Bootstrap capacitor charging circuit for GaN devices

• US 10,333,327 B2
• Filed: 04/24/2018
• Issued: 06/25/2019
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel Marvin, Sharma, Santosh, Zhang, Ju Jason
• Primary Examiner(s): Donovan, Lincoln D
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US15/961,723
• Publication Number:
  US 20190148961A1
• Time in Patent Office: 427 Days
• Field of Search: None
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02M 1/0048 : Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/088 : for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/155 : using semiconductor devices only
• CPC Class Codes: H02M 3/157 : with digital control
• CPC Class Codes: H02M 3/1584 : with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1588 : comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/102 : in field-effect transistor switches
• CPC Class Codes: H03K 19/018507 : Interface arrangements
• CPC Class Codes: H03K 3/012 : Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356017 : using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: Y02B 40/00 : Technologies aiming at improving the efficiency of home appliances, e.g. induction cooking or efficient technologies for refrigerators, freezers or dish washers
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Claims

1. A charging circuit comprising:

a GaN-based semiconductor circuit configured to allow current flow from a ground referenced power supply node to a first floating power supply terminal, wherein the semiconductor circuit comprises;

a first enhancement-mode transistor, comprising;

a gate configured to be controlled by a gate drive circuit control signal,

a source directly connected to the ground referenced power supply node, and

a drain directly connected to the first floating power supply terminal; and

a second enhancement-mode transistor, comprising;

a gate connected to the ground referenced power supply node,

a source directly connected to the ground referenced power supply node, and

a drain directly connected to the first floating power supply terminal.

2. The charging circuit of claim 1, wherein the semiconductor circuit is configured to be capable of operating with the first floating power supply terminal at a voltage that is at least 20 volts greater than a voltage of the ground referenced power supply node.

3. The charging circuit of claim 1, wherein the semiconductor circuit is used in conjunction with a half bridge circuit comprising:

a low side GaN-based transistor having a low side transistor control gate configured to receive a low side gate signal from a ground referenced gate drive circuit; and

a high side GaN-based transistor having a high side transistor control gate configured to receive a high side gate signal from a gate drive circuit that is referenced to a second floating power supply terminal.

4. The charging circuit of claim 3, wherein the second floating power supply terminal is a switch node of the half bridge circuit.

5. The charging circuit of claim 3, wherein a capacitor is connected between the first floating power supply terminal and the second floating power supply terminal.

6. The charging circuit of claim 3, wherein the gate drive circuit control signal is in phase with the low side gate signal.

7. The charging circuit of claim 3, further comprising a delay circuit configured to turn on the first enhancement-mode transistor after the low side GaN-based transistor turns on.

8. The charging circuit of claim 3, further comprising a delay circuit configured to turn off the first enhancement-mode transistor before the low side GaN-based transistor turns off.

9. An electronic power conversion component comprising:

a package base; and

one or more GaN-based dies secured to the package base, each including a charging circuit comprising;

a GaN-based semiconductor circuit configured to allow current flow from a ground referenced power supply node to a first floating power supply terminal, wherein the semiconductor circuit comprises;

a first enhancement-mode transistor, comprising;

a gate configured to be controlled by a gate drive circuit control signal,

a source directly connected to the ground referenced power supply node, and

a drain directly connected to the first floating power supply terminal; and

a second enhancement-mode transistor, comprising;

a gate connected to the ground referenced power supply node,

a source directly connected to the ground referenced power supply node, and

a drain directly connected to the first floating power supply terminal.

10. The component of claim 9, wherein the semiconductor circuit is configured to be capable of operating with the first floating power supply terminal at a voltage that is at least 20 volts greater than a voltage of the ground referenced power supply node.

11. The component of claim 9, wherein the semiconductor circuit is used in conjunction with a half bridge circuit comprising:

a low side GaN-based transistor having a low side transistor control gate configured to receive a low side gate signal from a ground referenced gate drive circuit; and

a high side GaN-based transistor having a high side transistor control gate configured to receive a high side gate signal from a gate drive circuit that is referenced to a second floating power supply terminal.

12. The component of claim 11, wherein the second floating power supply terminal is a switch node of the half bridge circuit.

13. The component of claim 11, wherein a capacitor is connected between the first floating power supply terminal and the second floating power supply terminal.

14. The component of claim 11, wherein the gate drive circuit control signal is in phase with the low side gate signal.

15. The component of claim 11, wherein each semiconductor circuit comprises a delay circuit configured to turn on the first enhancement-mode transistor after the low side GaN-based transistor turns on.

16. The component of claim 11, wherein each semiconductor circuit comprises a delay circuit configured to turn off the first enhancement-mode transistor before the low side GaN-based transistor turns off.

17. A method of using a charging circuit, the method comprising:

allowing current to flow from a ground referenced power supply node to a first floating power supply terminal with a semiconductor circuit, wherein the semiconductor circuit comprises;

a first enhancement-mode transistor, comprising;

a gate configured to be controlled by a gate drive circuit control signal,

a source directly connected to the ground referenced power supply node, and

a drain directly connected to the first floating power supply terminal,

wherein the first enhancement-mode transistor is configured to allow current to flow from the ground referenced power supply to the first floating power supply terminal in response to the gate drive circuit control signal; and

a second enhancement-mode transistor, comprising;

a gate connected to the ground referenced power supply node,

a source directly connected to the ground referenced power supply node, and

a drain directly connected to the first floating power supply terminal.

18. The method of claim 17, further comprising providing a potential to the first floating power supply terminal which is at least 20 volts greater than a voltage of the ground referenced power supply node.

19. The method of claim 17, wherein the first enhancement-mode transistor is configured to prevent current from flowing from the ground referenced power supply node to the first floating power supply terminal in response to the gate drive circuit control signal.

20. The method of claim 17, wherein the semiconductor circuit is used in conjunction with a half bridge circuit comprising the ground referenced power supply node and the first floating power supply terminal.