Tunable filters, cancellers, and duplexers based on passive mixers

• US 10,333,569 B2
• Filed: 09/15/2017
• Issued: 06/25/2019
• Est. Priority Date: 09/04/2015
• Status: Active Grant

• Current Assignee: North Carolina State University (University of North Carolina System)
• Original Assignee: North Carolina State University (University of North Carolina System)
• Inventors: Floyd, Brian Allan, Wilson, III, Charley Theodore, Bonner-Stewart, Jeffrey Franklin
• Primary Examiner(s): Trinh, Sonny
• Application Number:
  US15/706,327
• Publication Number:
  US 20180013459A1
• Time in Patent Office: 648 Days
• Field of Search: 455296, 455 78, 455307
• CPC Class Codes: H03D 2200/0074 using a resistive mixer or a passive mixer
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H03H 7/20 Two-port phase shifters providing an adjustable phase shift
• CPC Class Codes: H03H 7/463 Duplexers
• CPC Class Codes: H04B 1/1036 with automatic suppression of narrow band noise or interference, e.g. by using tuneable notch filters H04B1/123 takes precedence; filter circuits H03H
• CPC Class Codes: H04B 1/1081 Reduction of multipath noise by equalising H04B7/005
• CPC Class Codes: H04B 1/18 Input circuits, e.g. for coupling to an antenna or a transmission line coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H
• CPC Class Codes: H04L 7/0016 correction of synchronization errors

Abstract

Tunable filters, cancellers, and duplexers based on passive mixers. A tunable delay cell includes passive mixers electrically coupled together for receiving an input signal and outputting a delayed signal, each passive mixer comprising a plurality of mixer switches. The tunable delay includes a control circuit for providing, to each passive mixer, a respective plurality of local oscillator (LO) signals, one to each mixer switch of each passive mixer. The control circuit is configured to vary the LO signals to cause a target frequency band of the input signal to be delayed by a target delay time in propagating through the passive mixers.

Claims

1. A tunable delay cell comprising:

a plurality of passive mixers electrically coupled together for receiving an input signal and outputting a delayed signal, each passive mixer comprising a plurality of mixer switches; and

a control circuit for providing, to each passive mixer, a respective plurality of local oscillator (LO) signals, one to each mixer switch of each passive mixer;

wherein the control circuit is configured to vary the LO signals to cause a target frequency band of the input signal to be delayed by a target delay time in propagating through the passive mixers; and

wherein the passive mixers comprise;

a down-shifting mixer for receiving the input signal; and

an up-shifting mixer, electrically coupled to an output of the down-shifting mixer, for outputting the delayed signal.

2. The tunable delay cell of claim 1, comprising a baseband filter electrically coupled between the down-shifting mixer and the up-shifting mixer.

3. The tunable delay cell of claim 2, wherein the baseband filter is a bandpass filter and the bandpass filter, the down-shifting mixer, and the up-shifting mixer are configured so that a pass band of the bandpass filter matches the target frequency band of the input signal.

4. The tunable delay cell of claim 2, wherein the baseband filter comprises one or more capacitors.

5. The tunable delay cell of claim 1, wherein the control circuit is configured to vary the LO signals by reordering phases of the LO signals for coarse resolution of the target delay time.

6. The tunable delay cell of claim 1, wherein the control circuit comprises a delay circuit configured to vary the LO signals by offsetting respective clock signals supplied to the passive mixers for fine resolution of the target delay time.

7. The tunable delay cell of claim 6, wherein offsetting respective clock signals comprises offsetting the clock signals within a least significant bit (LSB) of a variable characterizing the target delay time as a mixer period.

8. The tunable delay cell of claim 6, wherein the delay circuit comprises one or more of:

a delay-locked loop, a switched delay line, and a tunable varactor.