HDR pixel array with double diagonal binning

• US 10,334,189 B1
• Filed: 06/06/2018
• Issued: 06/25/2019
• Est. Priority Date: 06/06/2018
• Status: Active Grant

• Current Assignee: Smartsens Technology (Cayman) Co., Ltd.
• Original Assignee: Smartsens Technology (Cayman) Co., Ltd.
• Inventors: Xu, Chen, Mo, Yaowu, Shao, Zexu, Zhang, Zhengmin, Ma, Weijian
• Primary Examiner(s): Aggarwal, Yogesh K
• Application Number:
  US16/001,145
• Time in Patent Office: 384 Days
• Field of Search: 348294-324
• CPC Class Codes: H04N 23/10 for generating image signals from different wavelengths
• CPC Class Codes: H04N 25/13 characterised by the spectral characteristics of the filter elements
• CPC Class Codes: H04N 25/46 by combining or binning pixels
• CPC Class Codes: H04N 25/60 Noise processing, e.g. detecting, correcting, reducing or removing noise
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/74 Circuitry for scanning or addressing the pixel array
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

An image sensor has a pixel cell array comprising clusters of pixel cell blocks each block having four pixel cells under the same microlens and filter wherein during readout electrical signals from two pixels positioned along a first diagonal are binned followed by binning the signals from two pixels positioned along the remaining second reverse diagonal in order to reduce spatial color artifacts associated with orthogonal binning schemes and minimize gaps or irregular spacing between optical centers within an image read out from the array of pixel cells.

Claims

1. An imaging system comprising:

an array of pixel cell clusters, each pixel cell cluster comprising four pixel cell blocks arranged in a two by two configuration, and each pixel cell block comprising four pixel cells arranged in a two by two configuration to form a first diagonally adjacent pair and a second reverse diagonally adjacent pair of pixel cells to form rows and columns of pixels;

a color filter with same color disposed over each pixel cell block wherein the four pixel cell blocks forming their associated cluster form a Bayer color filter array over each cluster;

a single plano-convex microlens disposed over the color filter and the four pixels of each pixel cell block; and

a control and readout circuit for each pixel cell block, wherein each pixel cell comprises a photodiode controlled by a transfer transistor and a transfer transistor control line, wherein the transfer transistors of the first diagonally adjacent pair of pixel cells share a first transfer transistor control line, and the transfer transistors of the second reverse diagonally adjacent pair of pixels share a second transfer transistor control line.

2. The imaging system of claim 1, wherein within each pixel cell block, the two horizontally adjacent pixel cells lying on a first row of pixel cells share a common floating drain, amplifier transistor, row select transistor, and connection to a first column line;

and wherein within each pixel cell block, the two horizontally adjacent pixel cells lying on a second row of pixel cells share a common floating drain, amplifier transistor, row select transistor, and connection to a second column line.

3. The imaging system of claim 1, wherein within each pixel cell block, the two diagonally adjacent pixel cells lying on two vertically positioned adjacent rows of pixel cells share a common floating drain, amplifier transistor, row select transistor, and connection to a first column line;

and wherein within each pixel, cell block the two reverse diagonally adjacent pixel cells lying on the two vertically positioned adjacent rows of pixel cells share a common floating drain, amplifier transistor, row select transistor, and connection to a second column line.

4. The imaging system of claim 1, further comprising an opaque light guide structure positioned between the microlenses, wherein the light guide is absent between the diagonally adjacent pixel cells and the reverse diagonally adjacent pixel cells comprising the pixel cell block.

5. A method for providing binning and readout of adjacent pixel cells within a two by two block of pixel cells which minimizes gaps or irregular spacing between optical centers within an image read out from an array of pixel cells, the method comprising the steps of:

providing an array of pixel cell clusters, each pixel cell cluster comprising four pixel cell blocks arranged in a two by two configuration and each pixel cell block comprising four pixel cells arranged in a two by two configuration to form a first diagonally adjacent pair and a second reverse diagonally adjacent pair of pixel cells to form rows and columns of pixels;

providing a color filter with same color disposed over each pixel cell block wherein the four pixel cell blocks forming their associated cluster form a Bayer color filter array over each cluster;

providing a single plano-convex microlens disposed over the color filter and the four pixels of each pixel cell block;

providing a control and readout circuit for each pixel cell block, wherein each pixel cell comprises a photodiode controlled by a transfer transistor and a transfer transistor control line, wherein the transfer transistors of the first diagonally adjacent pair of pixel cells share a first transfer transistor control line, and the transfer transistors of the second reverse diagonally adjacent pair of pixels share a second transfer transistor control line, and wherein within each pixel cell block the two horizontally adjacent pixel cells lying on a first row of pixel cells share a common floating drain, amplifier transistor, row select transistor, and connection to a first column line, and wherein within each pixel cell block the two horizontally adjacent pixel cells lying on a second row of pixel cells share a common floating drain, amplifier transistor, row select transistor, and connection to a second column line; and

focusing light from a target scene onto the pixel array and enabling the first transfer transistor control line to cause the electrical signals from the first diagonally adjacent pair of pixel cells to be read out simultaneously onto the first and second column lines, whereupon binning of the two electrical signals is subsequently completed and then enabling the second transfer transistor control line to cause the electrical signals from the second reverse diagonally adjacent pair of pixel cells to be read out simultaneously onto the first and second column lines whereupon binning of the two electrical signals is subsequently completed.

6. The method of claim 5, wherein combining the electrical signals on the first column line and on the second column line when the first transfer transistor control line is enabled comprises the binned signal representative of the first diagonally adjacent pair of pixel cells with an optical center coincident with the physical center of the first diagonally adjacent pair of pixel cells, and wherein combining the electrical signals on the first column line and on the second column line when the second transfer transistor control line is enabled comprises the binned signal representative of the second reverse diagonally adjacent pair of pixel cells with an optical center coincident with the physical center of the second reverse diagonally adjacent pair of pixel cells.

7. A method for providing binning and readout of adjacent pixel cells within a two by two block of pixel cells which minimizes gaps or irregular spacing between optical centers within an image read out from an array of pixel cells, the method comprising the steps of:

providing an array of pixel cell clusters, each pixel cell cluster comprising four pixel cell blocks arranged in a two by two configuration and each pixel cell block comprising four pixel cells arranged in a two by two configuration to form a first diagonally adjacent pair and a second reverse diagonally adjacent pair of pixel cells to form rows and columns of pixels;

providing a color filter with same color disposed over each pixel cell block wherein the four pixel cell blocks forming their associated cluster form a Bayer color filter array over each cluster;

providing a single plano-convex microlens disposed over the color filter and the four pixels of each pixel cell block;

providing a control and readout circuit for each pixel cell block wherein each pixel cell comprises a photodiode controlled by a transfer transistor and a transfer transistor control line wherein the transfer transistors of the first diagonally adjacent pair of pixel cells share a first transfer transistor control line and the transfer transistors of the second reverse diagonally adjacent pair of pixels share a second transfer transistor control line and wherein within each pixel cell block the two diagonally adjacent pixel cells lying on two vertically positioned adjacent rows of pixel cells share a common floating drain, amplifier transistor, row select transistor and connection to a first column line and wherein within each pixel cell block the two reverse diagonally adjacent pixel cells lying on the two vertically positioned adjacent rows of pixel cells share a common floating drain, amplifier transistor, row select transistor and connection to a second column line;

focusing light from a target scene onto the pixel array and enabling the first transfer transistor control line to cause immediate binning of the electrical signals from the first diagonally adjacent pair of pixel cells onto the first column line and then enabling the second transfer transistor control line to cause immediate binning of the electrical signals from the second reverse diagonally adjacent pair of pixel cells onto the second column line.

8. The method of claim 7, wherein combining the electrical signal on the first column line when the first transfer transistor control line is enabled with the electrical signal on the second column line when the second transfer transistor control line is enabled comprises a binned signal representative of the first diagonally adjacent pair of pixel cells combined with a binned signal representative of the second reverse diagonally adjacent pair of pixel cells with an optical center coincident with the physical center of the block of four pixels.