Highly accurate defect identification and prioritization of fault locations

• US 10,338,137 B1
• Filed: 07/20/2016
• Issued: 07/02/2019
• Est. Priority Date: 07/20/2016
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Chillarige, Sameer Chakravarthy, Malik, Anil, Singh, Sharjinder, Swenton, Joseph Michael
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US15/215,261
• Time in Patent Office: 1,077 Days
• Field of Search: 714738
• CPC Class Codes: G01R 31/317 Testing of digital circuits
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318307 computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
• CPC Class Codes: G01R 31/318314 Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages simulation software G01R31/318357; emulators G06F11/261
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318569 Error indication, logging circuits
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924

Abstract

A method for defect identification for an integrated circuit includes determining a defect ranking technique, applying at least two defect identification techniques and generating a defect report corresponding to each technique, comparing the defect reports and generating probable defect locations, prioritizing the probable defect locations according to the defect ranking technique; and generating a report of the prioritized probable defect locations.

Claims

1. A method for identification of locations of defects in a circuit, the method comprising:

applying, with a processor, a plurality of different defect analysis techniques to fault data associated with the circuit, wherein the plurality of defect analysis techniques includes per-fail scoring analysis, per-cycle scoring analysis, and per-pattern scoring analysis;

performing, with the processor, a plurality of different defect identification techniques on the applied plurality of defect analysis techniques, wherein the plurality of defect identification techniques are selected from a group that includes (i) circuit topology based fail partitioning and (ii) software based fail partitioning;

generating, with the processor, a defect report for each of the plurality of defect analysis techniques based on the performed defect identification techniques, wherein each defect report identifies at least one probable defect location;

performing, with the processor, a fault analysis on each of the identified probable defect locations in the defect reports, wherein a same probable defect location identified in a plurality of the defect reports is ranked higher than a probable defect location identified in only one of the defect reports; and

generating, with the processor, a report of the probable defect locations based on the fault analysis.

2. The method of claim 1, further comprising:

prioritizing the probable defect locations according to the defect ranking technique.

3. The method of claim 1, wherein the performing of the plurality of defect identification techniques includes iterating each of the defect identification techniques for a predetermined time.

4. The method of claim 1, wherein the performing of the plurality of defect identification techniques includes each defect identification technique being iterated for a unique length of time.

5. The method of claim 1, wherein each of the plurality of defect analysis techniques is associated with a different weighting.

6. The method of claim 1, wherein each of the plurality of defect analysis techniques is associated with a different priority.

16. The method of claim 1, wherein:

for per-fail scoring analysis;

faults in the fault data are scored on a failure by failure basis,

a failure location in a test pattern is marked as explained only if a circuit fault results in a measurement value indicative of the circuit fault at the failure location and matches a faulty behavior of the circuit at the failure location in the test pattern, and

credit is given to a fault when it explains a failing location in the failing pattern;

for per-cycle scoring analysis;

faults in the fault data are scored on a cycle by cycle basis,

a set of failure locations measured in a single scan clock cycle in a test pattern is marked as explained only if all the failure locations match a faulty behavior of the circuit in the single scan clock cycle for the test pattern, and

credit is given to a fault when it explains all failures in the single scan clock cycle in the test pattern;

for per-pattern scoring analysis,

faults in the fault data are scored on a pattern by pattern basis,

a set of all the failure locations measured in a test pattern is marked as explained when all the failure locations match a faulty behavior of the circuit in the test pattern, and

credit is given to a fault when it explains all failures in the test pattern.

7. A non-transitory computer readable medium containing program instructions for a diagnostics system, wherein execution of the program instructions by one or more processors of a computer system causes one or more processors to perform the following:

apply a plurality of different defect analysis techniques to fault data associated with a circuit, wherein the plurality of defect analysis techniques includes per-fail scoring analysis, per-cycle scoring analysis, and per-pattern scoring analysis;

perform a plurality of different defect identification techniques on the applied plurality of defect analysis techniques, wherein the plurality of defect identification techniques are selected from a group that includes (i) circuit topology based fail partitioning and (ii) software based fail partitioning;

generate a defect report corresponding to each of the plurality of defect analysis techniques based on the performed defect identification techniques, wherein each defect report identifies at least one probable defect location;

perform a fault analysis on each of the identified probable defect locations in the defect reports, wherein a same probable defect location identified in a plurality of the defect reports is ranked higher than a probable defect location identified in only one of the defect reports; and

generate a report of the probable defect locations based on the fault analysis.

8. The non-transitory computer readable medium of claim 7, further comprising:

prioritizing the probable defect locations according to the defect ranking technique.

9. The non-transitory computer readable medium of claim 7, wherein the performing of the plurality of defect identification techniques includes iterating each of the defect identification techniques for a predetermined time.

10. The non-transitory computer readable medium of claim 7, wherein the performing of the plurality of defect identification techniques includes each defect identification technique being iterated for a unique length of time.

11. The non-transitory computer readable medium of claim 7, wherein each of the plurality of defect analysis techniques is associated with a different weighting.

12. The non-transitory computer readable medium of claim 7, wherein each of the plurality of defect analysis techniques is associated with a different priority.

17. The computer readable medium of claim 7, wherein:

for per-fail scoring analysis;

faults in the fault data are scored on a failure by failure basis,

a failure location in a test pattern is marked as explained only if a circuit fault results in a measurement value indicative of the circuit fault at the failure location and matches a faulty behavior of the circuit at the failure location in the test pattern, and

credit is given to a fault when it explains a failing location in the failing pattern;

for per-cycle scoring analysis;

faults in the fault data are scored on a cycle by cycle basis,

a set of failure locations measured in a single scan clock cycle in a test pattern is marked as explained only if all the failure locations match a faulty behavior of the circuit in the single scan clock cycle for the test pattern, and

credit is given to a fault when it explains all failures in the single scan clock cycle in the test pattern;

for per-pattern scoring analysis,

faults in the fault data are scored on a pattern by pattern basis,

a set of all the failure locations measured in a test pattern is marked as explained when all the failure locations match a faulty behavior of the circuit in the test pattern, and

credit is given to a fault when it explains all failures in the test pattern.

13. An automatic test pattern generation (ATPG) system, the system comprising:

a processor, wherein the processor is configured to;

apply a plurality of different defect analysis techniques to fault data associated with a circuit, wherein the plurality of defect analysis techniques includes per-fail scoring analysis, per-cycle scoring analysis, and per-pattern scoring analysis;

perform a plurality of different defect identification techniques on the applied plurality of defect analysis techniques, wherein the plurality of defect identification techniques are selected from a group that includes (i) circuit topology based fail partitioning and (ii) software based fail partitioning;

generate a defect report corresponding to each of the plurality of defect analysis techniques based on the performed defect identification techniques, wherein each defect report identifies at least one probable defect location;

perform a fault analysis on each of the identified probable defect locations in the defect reports, wherein a same probable defect location identified in a plurality of the defect reports is ranked higher than a probable defect location identified in only one of the defect reports; and

generate a report of the probable defect locations based on the fault analysis.

14. The system of claim 13, wherein the plurality of defect analysis techniques are prioritized.

15. The system of claim 13, wherein the plurality of defect analysis techniques are weighted.

18. The system of claim 13, wherein:

for per-fail scoring analysis;

faults in the fault data are scored on a failure by failure basis,

a failure location in a test pattern is marked as explained only if a circuit fault results in a measurement value indicative of the circuit fault at the failure location and matches a faulty behavior of the circuit at the failure location in the test pattern, and

credit is given to a fault when it explains a failing location in the failing pattern;

for per-cycle scoring analysis;

faults in the fault data are scored on a cycle by cycle basis,

a set of failure locations measured in a single scan clock cycle in a test pattern is marked as explained only if all the failure locations match a faulty behavior of the circuit in the single scan clock cycle for the test pattern, and

credit is given to a fault when it explains all failures in the single scan clock cycle in the test pattern;

for per-pattern scoring analysis,

faults in the fault data are scored on a pattern by pattern basis,

a set of all the failure locations measured in a test pattern is marked as explained when all the failure locations match a faulty behavior of the circuit in the test pattern, and

credit is given to a fault when it explains all failures in the test pattern.