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Highly accurate defect identification and prioritization of fault locations

  • US 10,338,137 B1
  • Filed: 07/20/2016
  • Issued: 07/02/2019
  • Est. Priority Date: 07/20/2016
  • Status: Active Grant
First Claim
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1. A method for identification of locations of defects in a circuit, the method comprising:

  • applying, with a processor, a plurality of different defect analysis techniques to fault data associated with the circuit, wherein the plurality of defect analysis techniques includes per-fail scoring analysis, per-cycle scoring analysis, and per-pattern scoring analysis;

    performing, with the processor, a plurality of different defect identification techniques on the applied plurality of defect analysis techniques, wherein the plurality of defect identification techniques are selected from a group that includes (i) circuit topology based fail partitioning and (ii) software based fail partitioning;

    generating, with the processor, a defect report for each of the plurality of defect analysis techniques based on the performed defect identification techniques, wherein each defect report identifies at least one probable defect location;

    performing, with the processor, a fault analysis on each of the identified probable defect locations in the defect reports, wherein a same probable defect location identified in a plurality of the defect reports is ranked higher than a probable defect location identified in only one of the defect reports; and

    generating, with the processor, a report of the probable defect locations based on the fault analysis.

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