Highly accurate defect identification and prioritization of fault locations
First Claim
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1. A method for identification of locations of defects in a circuit, the method comprising:
- applying, with a processor, a plurality of different defect analysis techniques to fault data associated with the circuit, wherein the plurality of defect analysis techniques includes per-fail scoring analysis, per-cycle scoring analysis, and per-pattern scoring analysis;
performing, with the processor, a plurality of different defect identification techniques on the applied plurality of defect analysis techniques, wherein the plurality of defect identification techniques are selected from a group that includes (i) circuit topology based fail partitioning and (ii) software based fail partitioning;
generating, with the processor, a defect report for each of the plurality of defect analysis techniques based on the performed defect identification techniques, wherein each defect report identifies at least one probable defect location;
performing, with the processor, a fault analysis on each of the identified probable defect locations in the defect reports, wherein a same probable defect location identified in a plurality of the defect reports is ranked higher than a probable defect location identified in only one of the defect reports; and
generating, with the processor, a report of the probable defect locations based on the fault analysis.
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Abstract
A method for defect identification for an integrated circuit includes determining a defect ranking technique, applying at least two defect identification techniques and generating a defect report corresponding to each technique, comparing the defect reports and generating probable defect locations, prioritizing the probable defect locations according to the defect ranking technique; and generating a report of the prioritized probable defect locations.
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Citations
18 Claims
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1. A method for identification of locations of defects in a circuit, the method comprising:
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applying, with a processor, a plurality of different defect analysis techniques to fault data associated with the circuit, wherein the plurality of defect analysis techniques includes per-fail scoring analysis, per-cycle scoring analysis, and per-pattern scoring analysis; performing, with the processor, a plurality of different defect identification techniques on the applied plurality of defect analysis techniques, wherein the plurality of defect identification techniques are selected from a group that includes (i) circuit topology based fail partitioning and (ii) software based fail partitioning; generating, with the processor, a defect report for each of the plurality of defect analysis techniques based on the performed defect identification techniques, wherein each defect report identifies at least one probable defect location; performing, with the processor, a fault analysis on each of the identified probable defect locations in the defect reports, wherein a same probable defect location identified in a plurality of the defect reports is ranked higher than a probable defect location identified in only one of the defect reports; and generating, with the processor, a report of the probable defect locations based on the fault analysis. - View Dependent Claims (2, 3, 4, 5, 6, 16)
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7. A non-transitory computer readable medium containing program instructions for a diagnostics system, wherein execution of the program instructions by one or more processors of a computer system causes one or more processors to perform the following:
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apply a plurality of different defect analysis techniques to fault data associated with a circuit, wherein the plurality of defect analysis techniques includes per-fail scoring analysis, per-cycle scoring analysis, and per-pattern scoring analysis; perform a plurality of different defect identification techniques on the applied plurality of defect analysis techniques, wherein the plurality of defect identification techniques are selected from a group that includes (i) circuit topology based fail partitioning and (ii) software based fail partitioning; generate a defect report corresponding to each of the plurality of defect analysis techniques based on the performed defect identification techniques, wherein each defect report identifies at least one probable defect location; perform a fault analysis on each of the identified probable defect locations in the defect reports, wherein a same probable defect location identified in a plurality of the defect reports is ranked higher than a probable defect location identified in only one of the defect reports; and generate a report of the probable defect locations based on the fault analysis. - View Dependent Claims (8, 9, 10, 11, 12, 17)
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13. An automatic test pattern generation (ATPG) system, the system comprising:
a processor, wherein the processor is configured to; apply a plurality of different defect analysis techniques to fault data associated with a circuit, wherein the plurality of defect analysis techniques includes per-fail scoring analysis, per-cycle scoring analysis, and per-pattern scoring analysis; perform a plurality of different defect identification techniques on the applied plurality of defect analysis techniques, wherein the plurality of defect identification techniques are selected from a group that includes (i) circuit topology based fail partitioning and (ii) software based fail partitioning; generate a defect report corresponding to each of the plurality of defect analysis techniques based on the performed defect identification techniques, wherein each defect report identifies at least one probable defect location; perform a fault analysis on each of the identified probable defect locations in the defect reports, wherein a same probable defect location identified in a plurality of the defect reports is ranked higher than a probable defect location identified in only one of the defect reports; and generate a report of the probable defect locations based on the fault analysis. - View Dependent Claims (14, 15, 18)
Specification