Method and system for online program/erase count estimation

• US 10,338,983 B2
• Filed: 12/30/2016
• Issued: 07/02/2019
• Est. Priority Date: 12/30/2016
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Inventors: Jeon, Seungjune, Tabrizi, Haleh, Cullen, Andrew
• Primary Examiner(s): Lamarre, Guy J
• Application Number:
  US15/395,248
• Publication Number:
  US 20180189123A1
• Time in Patent Office: 914 Days
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/00 Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor G11C14/00 - G11C21/00 take precedence
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

In general, the technology relates to a method for managing persistent storage. The method includes selecting a sample set of physical addresses in a solid state memory module, and performing a garbage collection operation on the sample set of physical addresses. The method further includes, after the garbage collection operation, issuing a write request to the sample set of physical addresses, issuing a request read to the sample set of physical addresses to obtain a copy of the data stored in the sample set of physical addresses, determining an error rate in the copy of the data stored using an Error Correction Code codeword or known data in the write request, determining a calculated P/E cycle value for the SSMM using at least the error rate, and updating an in-memory data structure in a control module with the calculated P/E cycle value.

Claims

1. A method for managing persistent storage, the method comprising:

selecting a sample set of physical addresses in a solid state memory module (SSMM), wherein the sample set of physical addresses is associated with a region in the SSMM;

performing a garbage collection operation on the sample set of physical addresses;

after the garbage collection operation, issuing a write request to the sample set of physical addresses;

after issuing the write request, issuing a read request to the sample set of physical addresses to obtain a copy of data stored in the sample set of physical addresses;

determining an error rate in the copy of the data stored using at least one selected from a group consisting of an Error Correction Code (ECC) codeword and, known data in the write request;

determining a calculated P/E cycle value for the SSMM using at least the error rate; and

updating an in-memory data structure in a control module with the calculated P/E cycle value.

2. The method of claim 1, further comprising:

servicing at least one read request using the calculated P/E cycle value.

3. The method of claim 1, further comprising:

prior to the selecting;

determining that the region in the SSMM is not associated with a P/E cycle value.

4. The method of claim 1, further comprising:

prior to the selecting;

detecting a P/E cycle value anomaly in a P/E cycle value associated with the region.

5. The method of claim 4, wherein detecting the P/E cycle value anomaly comprises determining that a difference in the P/E cycle value for the region and a P/E cycle value for a second region in the SSMM is greater than an anomaly threshold.

6. The method of claim 1, further comprising:

servicing at least one selected from a group consisting of a read request and a write request by the SSMM while determining the error rate.

7. The method of claim 1, wherein the error rate is a failed bit count (FBC).

8. The method of claim 7, wherein the FBC is a mean FBC of all FBCs determined from the copy of the data.

9. The method of claim 1, wherein the SSMM is one of a plurality of SSMM in a storage module.

10. The method of claim 1, wherein the SSMM comprises NAND flash.

11. The method of claim 1, wherein performing the garbage collection operation on the sample set of physical addresses comprises:

determining that data stored in a physical address in the sample set of physical addresses is live;

selecting a new physical address, wherein the new physical address is associated with a known P/E cycle value; and

storing a copy of the data at the new physical address.

12. The method of claim 11, wherein the new physical address is located in a second SSMM in a second storage module, wherein the SSMM is located in a storage module.

13. The method of claim 1, wherein the calculated P/E cycle value represents a P/E cycle value range.

14. A non-transitory computer readable medium comprising computer readable program code, which when executed by a computer processor enables the computer processor to:

select a sample set of physical addresses in a solid state memory module (SSMM), wherein the sample set of physical addresses is associated with a region in the SSMM;

perform a garbage collection operation on the sample set of physical addresses;

after the garbage collection operation, issue a write request to the sample set of physical addresses;

after issuing the write request, issue a read request to the sample set of physical addresses to obtain a copy of data stored in the sample set of physical addresses;

determine an error rate in the copy of the data stored using at least one selected from a group consisting of an Error Correction Code (ECC) codeword and, known data in the write request;

determine a calculated P/E cycle value for the SSMM using at least the error rate; and

update an in-memory data structure in a control module with the calculated P/E cycle value.

15. The non-transitory computer readable medium of claim 14 further comprising computer readable program code, which when executed by the computer processor enables the computer processor to:

service at least one read request using the calculated P/E cycle value.

16. The non-transitory computer readable medium of claim 14 further comprising computer readable program code, which when executed by the computer processor enables the computer processor to:

service at least one selected from a group consisting of a read request and a write request by the SSMM while determining the error rate.