Non-intrusive monitoring and control of integrated circuits

• US 10,339,022 B2
• Filed: 07/10/2018
• Issued: 07/02/2019
• Est. Priority Date: 07/04/2013
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Olgiati, Andrea, Baker, Matthew Pond, Teig, Steven
• Primary Examiner(s): Tran, Anh Q
• Application Number:
  US16/032,050
• Publication Number:
  US 20180322026A1
• Time in Patent Office: 357 Days
• Field of Search: None
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 11/3003 Monitoring arrangements specially adapted to the computing system or computing system component being monitored
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.

Claims

1. A tangible, non-transitory, machine-readable medium, comprising machine-readable instructions to:

establish a connection to an electrical device that comprises a programmable logic device;

send an incremental configuration data over the connection, wherein the incremental configuration data comprises a trigger condition, wherein the incremental configuration data is based at least in part on a first configuration data previously loaded on the programmable logic device, and wherein the incremental configuration data is configured to cause the programmable logic device of the electrical device to generate debug information upon meeting the trigger condition; and

receive the debug information from the programmable logic device over the connection.

2. The machine-readable medium of claim 1, wherein the connection comprises a network connection.

3. The machine-readable medium of claim 2, wherein the network connection comprises an Ethernet protocol.

4. The machine-readable medium of claim 1, wherein the electrical device comprises a controller coupled to the programmable logic device.

5. The machine-readable medium of claim 4, comprising instructions to request the electrical device to generate a second configuration data to the programmable logic device using a configuration protocol, wherein the second configuration data is based at least in part on the first configuration data and the incremental configuration data.

6. The machine-readable medium of claim 1, wherein the electrical device is disposed in a data center.

7. The machine-readable medium of claim 1, wherein the trigger condition comprises a data capture condition, and wherein generating the debug information comprises collecting and storing data in a buffer of the programmable logic device based on an evaluation of the data capture conditions.

8. A method, comprising:

generating, in a configuration device, incremental configuration data for a field programmable gate array (FPGA) device based, at least in part, on first configuration data and at least one trigger condition;

establishing a connection between the configuration device and the FPGA device that comprises the first configuration data;

sending the incremental configuration data via the connection to reprogram the FPGA device, wherein the reprogrammed FPGA device is configured to cause the FPGA device to generate capture data that comprises a stored data sample of a state of the FPGA device upon meeting the at least one trigger condition; and

receiving the capture data from the FPGA device via the connection.

9. The method of claim 8, wherein sending the incremental configuration data comprise sending the incremental configuration data to a processor coupled to a controller that is coupled to the FPGA device via a configuration cable.

10. The method of claim 9, wherein the incremental configuration data comprises a JTAG instruction.

11. The method of claim 8, wherein the connection comprises an Ethernet connection.

12. The method of claim 8, wherein the incremental configuration data is based, at least in part, on monitoring instructions comprising monitoring a signal of the FPGA device using a monitor network of the FPGA device.

13. The method of claim 12, wherein the monitoring network comprises a JTAG network configured to monitor a JTAG instruction.

14. The method of claim 8, wherein the at least one trigger condition comprises a state machine.

15. The method of claim 8, comprising generating second incremental instructions via the connection, wherein the second incremental instructions are based at least in part on the captured data.

16. An electronic device comprising:

a programmable logic device; and

a controller coupled to the programmable logic device via a configuration link, wherein the controller is configured to;

receive incremental instructions to program the programmable logic device from a computing device coupled to the electronic device via a network connection, wherein the incremental instructions comprise at least one trigger condition;

configure the programmable logic device to generate debug information upon meeting the at least one trigger condition;

receive the debug information from the programmable logic device via the configuration link; and

transmit the debug information to the computing device via the network connection.

17. The electronic device of claim 16, wherein the controller comprises a processor.

18. The electronic device of claim 16, wherein the electronic device is a data center device.

19. The electronic device of claim 16, wherein the electronic device comprises a system on chip that comprises the programmable logic device, and wherein the programmable logic device is not directly accessible by the computing device.

20. The electronic device of claim 16, wherein the configuration link comprises a JTAG link, and wherein the network connection comprises an internet-based protocol.