System and method for individual addressing

• US 10,339,071 B2
• Filed: 12/10/2018
• Issued: 07/02/2019
• Est. Priority Date: 09/29/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bell, Debra, Glendenning, Paul, Brown, David R., Noyes, Harold B
• Primary Examiner(s): Tseng, Cheng Yuan
• Application Number:
  US16/192,509
• Publication Number:
  US 20190087360A1
• Time in Patent Office: 204 Days
• Field of Search: None
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 2213/2802 DMA using DMA transfer descriptors

Abstract

In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

Claims

1. A device comprising:

a bus interface; and

a plurality of state machine engines connected to the bus interface in a rank, wherein each of the plurality of state machine engines is configured to analyze data and to receive a respective address of a plurality of addresses from the bus interface for loading prior to executing a command from a processor or an instruction buffer, wherein the bus interface comprises a processor, an indirect address storage (IAS), and a multiplexer configured to switch to transmit the respective address of the plurality of addresses comprising an indirect address stored in the IAS when an indirect action is issued by the processor and an enable bit stored in the IAS is set.

2. The device of claim 1, wherein each respective address of the plurality of addresses comprises a direct address, an indirect address, or a dummy address.

3. The device of claim 1, wherein, when at least one respective address of the plurality of addresses comprises an indirect address, the indirect address is automatically incremented by the buffer interface.

4. The device of claim 1, wherein the multiplexer is configured to transmit the respective address of the plurality of addresses comprising a dummy address when the indirect action is issued by the processor and the enable bit stored in the IAS is deselected.

6. The device of claim 1, wherein a first state machine engine of the plurality of state machine engines is configured to execute the command at a first state machine engine address corresponding to a first address of the plurality of addresses.

7. The device of claim 6, wherein a second state machine engine of the plurality of state machine engines is configured to execute the command at second state machine engine address corresponding to a second address of a plurality of addresses.

8. The device of claim 7, wherein the first state machine engine and the second state machine engine are configured to execute the command in a same bus cycle.

5. A device comprising:

a bus interface; and

a plurality of state machine engines connected to the bus interface in a rank, wherein each of the plurality of state machine engines is configured to analyze data and to receive a respective address of a plurality of addresses from the bus interface for loading prior to executing a command from a processor or an instruction buffer, wherein the bus interface comprises a processor, a direct address storage (DAS), and a multiplexer configured to switch to transmit the respective address of the plurality of addresses comprising a direct address stored in the DAS when the multiplexer is set to transmit an output from the DAS.