Timing exact design conversions from FPGA to ASIC

• US 10,339,245 B2
• Filed: 01/16/2017
• Issued: 07/02/2019
• Est. Priority Date: 07/08/2002
• Status: Expired due to Fees

• Current Assignee: Liberty Patents LLC
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US15/407,242
• Publication Number:
  US 20170124241A1
• Time in Patent Office: 897 Days
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks
• CPC Class Codes: H10B 10/10 SRAM devices comprising bipolar components

Abstract

A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.

Claims

1. A method comprising:

accessing programming data for a programmable logic design to meet a plurality of design specifications; and

altering a programming data layer of the programmable logic design to form a hard-wired design that meets the plurality of design specifications, said altering including;

based on the programming data, determining a plurality of interconnects between the programming data layer and at least one of a plurality of input programming nodes of a programmable circuit layer of the programmable logic design and determining a plurality of individual logic values provided by a respective one of the plurality of interconnects; and

based on the plurality of individual logic values, replacing the programming data layer with a wire pattern layer hard-wired to a first portion of the plurality of interconnects to provide a logic high and hard-wired to a second portion of the plurality of interconnects to provide a logic low.

2. The method of claim 1, wherein the programmable logic design comprises a logic functionality performed by the programmable circuit layer, a timing characteristic, and a base die size.

3. The method of claim 2, wherein the logic functionality performed by the programmable circuit layer is one of unchanged by said altering or substantially unchanged by said altering.

4. The method of claim 2, wherein the timing characteristic is one of unchanged by said altering or substantially unchanged by said altering, and wherein the base die size is unchanged by said altering.

5. The method of claim 2, further comprising:

accessing other programming data for the programmable logic design to meet a plurality of other design specifications; and

altering the programming data layer of the programmable logic design to form other hard-wired design that meets the plurality of other design specifications, said altering the programming data layer of the programmable logic design to form other hard-wired design including;

based on the other programming data, determining a plurality of other interconnects between the programming data layer and at least one of the plurality of input programming nodes of the programmable circuit layer of the programmable logic design and determining a plurality of other individual logic values provided by a respective one of the plurality of other interconnects; and

based on the plurality of other individual logic values, replacing the programming data layer with other wire pattern layer hard-wired to a portion of the plurality of other interconnects to provide the logic high and hard-wired to another portion of the plurality of other interconnects to provide the logic low.

6. The method of claim 5, wherein the logic functionality performed by the programmable circuit layer and the timing characteristic are one of unchanged by said altering the programming data layer of the programmable logic design to form other hard-wired design or substantially unchanged by said altering the programming data layer of the programmable logic design to form other hard-wired design, and wherein the base die size is unchanged by said altering the programming data layer of the programmable logic design to form other hard-wired design.

7. A plurality of semiconductor devices comprising:

a programmable logic device including a first programming data layer, a first programmable circuit layer comprising a plurality of first input programming nodes, and a plurality of first interconnects between the first programming data layer and at least one of the plurality of first input programming nodes, wherein the programmable logic device is configured to receive programming data to meet a plurality of design specifications; and

a hard-wired logic device configured to meet the plurality of design specifications and including;

a second programmable circuit layer with common design relative to the first programmable circuit layer and comprising a plurality of second input programming nodes;

a wire pattern layer based on the programming data; and

a plurality of second interconnects between the wire pattern layer and at least one of the plurality of second input programming nodes and with common design relative to the plurality of first interconnects, wherein the wire pattern layer is hard-wired to a first portion of the plurality of second interconnects to provide a logic high and is hard-wired to a second portion of the plurality of second interconnects to provide a logic low.

8. The plurality of semiconductor devices of claim 7, wherein the programmable logic device comprises a first logic functionality performed by the first programmable circuit layer, a first timing characteristic, and a first base die size, and wherein the hard-wired logic device comprises a second logic functionality performed by the second programmable circuit layer, a second timing characteristic, and a second base die size.

9. The plurality of semiconductor devices of claim 8, wherein the first logic functionality performed by the first programmable circuit layer is one of identical or substantially identical to the second logic functionality performed by the second programmable circuit layer.

10. The plurality of semiconductor devices of claim 8, wherein the first timing characteristic is one of identical or substantially identical to the second timing characteristic, and wherein the first base die size is identical to the second base die size.

11. The plurality of semiconductor devices of claim 8, wherein the programmable logic device is configured to receive other programming data to meet a plurality of other design specifications, and further comprising:

other hard-wired logic device configured to meet the plurality of other design specifications and including;

other programmable circuit layer with common design relative to the first programmable circuit layer and comprising a plurality of other input programming nodes;

other wire pattern layer based on the other programming data; and

a plurality of other interconnects between the other wire pattern layer and at least one of the plurality of other input programming nodes and with common design relative to the plurality of first interconnects, wherein the other wire pattern layer is hard-wired to a portion of the plurality of other interconnects to provide the logic high and is hard-wired to another portion of the plurality of other interconnects to provide the logic low.

12. The plurality of semiconductor devices of claim 11, wherein the other hard-wired logic device comprises other logic functionality performed by the other programmable circuit layer, other timing characteristic, and other base die size.

13. The plurality of semiconductor devices of claim 12, wherein the first logic functionality performed by the first programmable circuit layer is one of identical or substantially identical to the other logic functionality performed by the other programmable circuit layer, wherein the first timing characteristic is one of identical or substantially identical to the other timing characteristic, and wherein the first base die size is identical to the other base die size.

14. A non-transitory computer-readable storage device comprising a plurality of computer-executable instructions stored therein, wherein the plurality of computer-executable instructions comprise:

instructions to provide a programmable logic design including a first programming data layer, a first programmable circuit layer comprising a plurality of first input programming nodes, and a plurality of first interconnects between the first programming data layer and at least one of the plurality of first input programming nodes;

instructions to provide programming data for the programmable logic design to meet a plurality of design specifications; and

instructions to provide a hard-wired logic design configured to meet the plurality of design specifications and including;

a second programmable circuit layer with common design relative to the first programmable circuit layer and comprising a plurality of second input programming nodes;

a wire pattern layer based on the programming data; and

a plurality of second interconnects between the wire pattern layer and at least one of the plurality of second input programming nodes and with common design relative to the plurality of first interconnects, wherein the wire pattern layer is hard-wired to a first portion of the plurality of second interconnects to provide a logic high and is hard-wired to a second portion of the plurality of second interconnects to provide a logic low.

15. The non-transitory computer-readable storage device of claim 14, wherein the programmable logic design comprises a first logic functionality performed by the first programmable circuit layer, a first timing characteristic, and a first base die size, and wherein the hard-wired logic design comprises a second logic functionality performed by the second programmable circuit layer, a second timing characteristic, and a second base die size.

16. The non-transitory computer-readable storage device of claim 15, wherein the first logic functionality performed by the first programmable circuit layer is one of identical or substantially identical to the second logic functionality performed by the second programmable circuit layer.

17. The non-transitory computer-readable storage device of claim 15, wherein the first timing characteristic is one of identical or substantially identical to the second timing characteristic, and wherein the first base die size is identical to the second base die size.

18. The non-transitory computer-readable storage device of claim 15, wherein the programmable logic design is configured to receive other programming data to meet a plurality of other design specifications, and wherein the computer-executable instructions further comprise:

instructions to provide other hard-wired logic design configured to meet the plurality of other design specifications and including;

other programmable circuit layer with common design relative to the first programmable circuit layer and comprising a plurality of other input programming nodes;

other wire pattern layer based on the other programming data; and

a plurality of other interconnects between the other wire pattern layer and at least one of the plurality of other input programming nodes and with common design relative to the plurality of first interconnects, wherein the other wire pattern layer is hard-wired to a portion of the plurality of other interconnects to provide the logic high and is hard-wired to another portion of the plurality of other interconnects to provide the logic low.

19. The non-transitory computer-readable storage device of claim 18, wherein the other hard-wired logic design comprises other logic functionality performed by the other programmable circuit layer, other timing characteristic, and other base die size.

20. The non-transitory computer-readable storage device of claim 19, wherein the first logic functionality performed by the first programmable circuit layer is one of identical or substantially identical to the other logic functionality performed by the other programmable circuit layer, wherein the first timing characteristic is one of identical or substantially identical to the other timing characteristic, and wherein the first base die size is identical to the other base die size.