Modified design rules to improve device performance

• US 10,339,248 B2
• Filed: 12/20/2017
• Issued: 07/02/2019
• Est. Priority Date: 09/10/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lum, Annie, Tao, Derek C., Lee, Cheng Hung, Lu, Chung-Ji, Cheng, Hong-Chen, Agrawal, Vineet Kumar, Kim, Keun-Young, Cho, Pyong Yun
• Primary Examiner(s): Alam, Mohammed
• Application Number:
  US15/848,333
• Publication Number:
  US 20180113973A1
• Time in Patent Office: 559 Days
• Field of Search: 716122
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.

Claims

1. A method, comprising:

designing a layout of gate structures and diffusion regions of a plurality of active devices;

identifying an edge device of the plurality of active devices;

adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout; and

fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device,

wherein the dummy device shares a diffusion region with the edge device, and

a gate structure of the dummy device is one of two dummy gate structures added next to the edge device, and the edge device has a gate structure and a diffusion region.

2. The method of claim 1, further comprising deactivating the dummy device.

3. The method of claim 1, wherein the gate structure of the dummy device has a first gate length and the gate structure of the edge device has a second gate length different than the first gate length.

4. The method of claim 3, wherein the dummy gate structure has a gate length equal to the first gate length or the second gate length.

5. The method of claim 1, wherein adding the dummy device comprises extending the diffusion region of the edge device to meet the dummy device, and adding an additional diffusion region on a second side of the dummy device opposite the edge device.

6. The method of claim 5, wherein adding the additional diffusion region on the second side of the dummy device comprises adding the additional diffusion region having a length less than a length of the diffusion region shared with the edge device.

7. The method of claim 1, further comprising removing at least one dummy gate structure, so that a single dummy gate structure is next to the dummy device.

8. The method of claim 1, wherein designing the layout of gate structures comprises joining a first device region to a second device region, and

adding the dummy device comprises adding a first dummy device next to an edge device of the first device region and adding a second dummy device next to an edge device of the second device region.

9. The method of claim 8, further comprising removing at least one dummy gate structure resulting in a single dummy gate structure being between the first dummy device and the second dummy device.

10. A method, comprising:

designing a layout of gate structures and diffusion regions of a semiconductor device;

identifying neighboring gate structures having different gate lengths, the neighboring gate structures including a first gate structure having a first gate length and a second gate structure having a second gate length less than the first gate length;

inserting a dummy device between the first gate structure and the second gate structure resulting in a modified layout, wherein the dummy device has one of the first gate length or the second gate length; and

fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of the semiconductor device.

11. The method of claim 10, further comprising deactivating the dummy device.

12. The method of claim 10, further comprising:

extending a diffusion region of the first gate structure having a first width to the dummy device; and

adding an additional diffusion region having the first width between a diffusion region of the second gate structure and the dummy device.

13. The method of claim 10, further comprising:

extending a diffusion region of the second gate structure having a first width to the dummy device; and

adding an additional diffusion region having the first width between a diffusion region of the first gate structure and the dummy device.

14. The method of claim 10, further comprising:

extending a diffusion region of the first gate structure having a first width to the dummy device; and

extending a diffusion region of the second gate structure having a second width to the dummy device, wherein the first width is different from the second width.

15. A method, comprising:

identifying a first gate structure and a second gate structure of a set of gate structures, the first gate structure having a first gate length and the second gate structure having a second gate length different than the first gate length;

inserting a dummy device between the first gate structure and the second gate structure resulting in a modified layout;

extending a first diffusion region of the first gate structure to a first side of the dummy device; and

fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of an integrated circuit.

16. The method of claim 15, further comprising:

adding an additional diffusion region between a second side of the dummy device and a second diffusion region of the second gate structure, the first diffusion region and the additional diffusion region having a same width.

17. The method of claim 15, further comprising:

extending a second diffusion region of the second gate structure to a second side of the dummy device, the first diffusion region and the second diffusion region having different widths.

18. The method of claim 15, further comprising deactivating the dummy device.

19. The method of claim 15, further comprising:

designing a layout of the integrated circuit having the set of gate structures and the first diffusion region.

20. The method of claim 15, wherein the dummy device has one of the first gate length or the second gate length.