Semiconductor device

• US 10,339,335 B2
• Filed: 08/20/2018
• Issued: 07/02/2019
• Est. Priority Date: 08/15/2013
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Sawada, Seiji
• Primary Examiner(s): Chang, Kenneth W
• Application Number:
  US16/105,231
• Publication Number:
  US 20180357441A1
• Time in Patent Office: 316 Days
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/6218 to a system of files or objects, e.g. local or distributed file system or database
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: G06F 3/0623 in relation to content
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1087 Data input latches

Abstract

A semiconductor device includes a first storage unit including twin cells which are electrically rewritable and complementarily store 1-bit data based on a difference in a threshold voltage, a second storage unit including a memory cell which is electrically rewritable, data stored in the memory cell being erased when data in the twin cells is erased, at least one scrambler subjecting first data to a scramble processing by using scramble data to generate second data, a first write circuit which writes the second data into the twin cells in the first storage unit, a second write circuit which writes the scramble data into the memory cell in the second storage unit, and at least one descrambler subjecting the second data read from the first storage unit to a descramble processing by using the scramble data read from the second storage unit.

Claims

1. A semiconductor device, comprising:

a first storage unit including twin cells which are electrically rewritable and complementarily store 1-bit data based on a difference in a threshold voltage;

a second storage unit including a memory cell which is electrically rewritable, data stored in the memory cell being erased when data in the twin cells is erased;

at least one scrambler subjecting first data to a scramble processing by using scramble data to generate second data;

a first write circuit which writes the second data into the twin cells in the first storage unit;

a second write circuit which writes the scramble data into the memory cell in the second storage unit; and

at least one descrambler subjecting the second data read from the first storage unit to a descramble processing by using the scramble data read from the second storage unit,

wherein the second storage unit includes a plurality of single cells each consisting of one memory cell and storing 1 bit of the scramble data, and the plurality of single cells redundantly store 1 bit of the scramble data, and

wherein the semiconductor device further comprises a sense amplifier including one input terminal simultaneously connected to a plurality of bit lines connected to the plurality of single cells and another terminal connected to a constant current source circuit.

2. A semiconductor device, including:

a first storage unit including twin cells which are electrically rewritable and complementarily store 1-bit data based on a difference in a threshold voltage;

a second storage unit including a memory cell which is electrically rewritable, data stored in the memory cell being erased when data n the twin cells is erased;

at least one scrambler subjecting first data to a scramble processing by using scramble data to generate second data;

a first write circuit which writes the second data into the twin cells in the first storage unit;

a second write circuit which writes the scramble data into the memory cell in the second storage unit; and

at least one descrambler subjecting the second data read from the first storage unit to a descramble processing by using the scramble data read from the second storage unit,

wherein the second storage unit includes a plurality of sets of twin cells each including two memory cells and storing 1 bit of the scramble data, and the plurality of sets of twin cells redundantly store 1 bit of the scramble data, and

wherein the semiconductor device further comprises a determination circuit which sends, when values for 1 bit read from the plurality of sets of twin cells are all identical, an identical value to the at least one descrambler, and sends, when there is a value for 1 bit different from other values for 1 bit read from the plurality of sets of twin cells, a value lower in frequency to the at least one descrambler.

3. A semiconductor device, comprising:

a first storage unit including twin cells which are electrically rewritable and complementarily store 1-bit data based on a difference in a threshold voltage;

a second storage unit including a memory cell which is electrically rewritable, data stored in the memory cell being erased when data in the twin cells is erased;

at least one scrambler subjecting first data to a scramble processing by using scramble data to generate second data;

a first write circuit which writes the second data into the twin cells in the first storage unit;

a second write circuit which writes the scramble data into the memory cell in the second storage unit; and

at least one descrambler subjecting the second data read from the first storage unit to a descramble processing by using the scramble data read from the second storage unit,

wherein the at least one scrambler includes a plurality of scramblers provided for respective columns in the first storage unit,

wherein each of the plurality of scramblers subjects write data of 1 bit into twin cells in a corresponding column to the scramble processing by using the scramble data,

wherein the at least one descrambler includes a plurality of descramblers provided for respective columns in the first storage unit, and

wherein each of the plurality of descramblers subjects the data of 1 bit read from the twin cells in the corresponding column to the descramble processing by using the scramble data read from the second storage unit.

4. The semiconductor device according to claim 3, wherein the scramble data includes a plurality of bits,

wherein each of the plurality of scramblers subjects write data of I bit into the twin cells in the corresponding column to the scramble processing by using 1 bit corresponding to the column among the plurality of bits constituting the scramble data, and

wherein each of the plurality of descramblers subjects the data of I bit read from the twin cells in the corresponding column to the descramble processing by using the 1 bit corresponding to the column among the plurality of bits constituting the scramble data.

5. A semiconductor device, comprising:

a first storage unit including twin cells which are electrically rewritable and complementarily store 1-bit data based on a difference in a threshold voltage;

a second storage unit including a memory cell which is electrically rewritable, data stored in the memory cell being erased when data in the twin cells is erased;

at least one scrambler subjecting first data to a scramble processing by using scramble data to generate second data;

a first write circuit which writes the second data into the twin cells in the first storage unit;

a second write circuit which writes the scramble data into the memory cell in the second storage unit; and

at least one descrambler subjecting the second data read from the first storage unit to a descramble processing by using the scramble data read from the second storage unit,

wherein the at least one scrambler includes a scrambler commonly provided for a plurality of columns in the first storage unit,

wherein the scrambler subjects write data of 1 bit into the twin cells to the scramble processing by using the scramble data,

wherein the at least one descrambler includes a descrambler commonly provided for a plurality of columns in the first storage unit, and

wherein the descrambler subjects the data of 1 bit read from the twin cells to the descramble processing by using the scramble data read from the second storage unit.

6. The semiconductor device according to claim 5, wherein the scramble data includes a plurality of bits,

wherein the scrambler subjects write data of 1 bit into the twin cells to the scramble processing by using 1 bit corresponding to a column of the twin cells among the plurality of bits constituting the scramble data, and

wherein the descrambler subjects the data of 1 bit read from the twin cells to the descramble processing by using the 1 bit corresponding to the column of the twin cells among the plurality of bits constituting the scramble data.

7. The semiconductor device according to claim 5, further comprising:

a plurality of sets of a data input pin and a data output pin; and

the scrambler and the descrambler for each set of the data input pin and the data output pin,

wherein a plurality of the scramblers perform the scramble processing by using identical scramble data, and a plurality of the descramblers perform the descramble processing by using the identical scramble data.