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Implementation of ResNet in a CNN based digital integrated circuit

  • US 10,339,445 B2
  • Filed: 02/14/2018
  • Issued: 07/02/2019
  • Est. Priority Date: 10/10/2016
  • Status: Active Grant
First Claim
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1. A digital integrated circuit for feature extraction comprising:

  • a plurality of cellular neural networks (CNN) processing engines operatively coupled to at least one input/output data bus, the plurality of CNN processing engines being connected in a loop with a clock-skew circuit, each CNN processing engine comprising;

    a CNN processing block configured for simultaneously obtaining convolution operations results using input data and pre-trained filter coefficients of a plurality of convolutional layers including at least one set of three particular convolutional layers for performing equivalent operations of a combination of first and second original convolutional layers followed by a short path, the equivalent operations containing convolutional operations of the first and the second original convolutional layers followed by element-wise add operations with an input that contains N feature maps and an output also contains N feature maps, each of the first and the second original convolutional layers contains N×

    N of 3×

    3 filter kernels, where N is a positive integer;

    a first set of memory buffers operatively coupling to the CNN processing block for storing the input data; and

    a second set of memory buffers operative coupling to the CNN processing block for storing the pre-trained filter coefficients;

    wherein first of the three particular convolutional layers contains 2N×

    N of 3×

    3 filter kernels formed by placing said N×

    N of 3×

    3 filter kernels of the first original convolutional layer in left side and N×

    N of 3×

    3 filter kernels of an identity-value convolutional layer in right side.

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