Signal processing apparatus
First Claim
1. A signal processing apparatus comprising:
- a first memory which stores plural pieces of coefficient data used for implementing a filter algorithm and containing plural coefficient data sets as many as a number corresponding to a filter order of the filter algorithm for at least one sort of filter algorithm of a variable filter order;
a second memory which stores input data sets from a last sample to a sample before the (filter order-1)-th sample for every filter algorithm as delay data sets; and
a processor which receives plural pieces of input data to be subjected to the filter algorithm, executes the filter algorithm using the plural pieces of coefficient data stored in the first memory and the plural pieces of received input data as many times as a number corresponding to a designated filter order, and outputs an execution result of the filter algorithm, in which filter algorithm each piece of coefficient data and each piece of input data are multiplied together and resultant products are summed up, and further, successively receives the coefficient data stored in the first memory and current input data stored in the second memory, repeatedly implements a first-order filter algorithm by time division processing of a dividing time length corresponding to the filter order, and outputs output-data within each sampling period.
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Abstract
A signal processing apparatus has a first memory in which plural pieces of FIR coefficient data used for implementing an FIR filter algorithm are stored, a second memory which stores plural pieces of input data to be subjected to the FIR filter algorithm, and a processor implements the FIR filter algorithm using the plural pieces of FIR coefficient data stored in the first memory and the plural pieces of input data stored in the second memory as many times as the number corresponding to a designated filter order, in which filter algorithm each piece of coefficient data and each piece of input data are multiplied together and resultant products are summed up. The signal processing apparatus is provided, which can implement plural sorts of FIR filter algorithms of filter order which can be changed flexibly.
13 Citations
15 Claims
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1. A signal processing apparatus comprising:
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a first memory which stores plural pieces of coefficient data used for implementing a filter algorithm and containing plural coefficient data sets as many as a number corresponding to a filter order of the filter algorithm for at least one sort of filter algorithm of a variable filter order; a second memory which stores input data sets from a last sample to a sample before the (filter order-1)-th sample for every filter algorithm as delay data sets; and a processor which receives plural pieces of input data to be subjected to the filter algorithm, executes the filter algorithm using the plural pieces of coefficient data stored in the first memory and the plural pieces of received input data as many times as a number corresponding to a designated filter order, and outputs an execution result of the filter algorithm, in which filter algorithm each piece of coefficient data and each piece of input data are multiplied together and resultant products are summed up, and further, successively receives the coefficient data stored in the first memory and current input data stored in the second memory, repeatedly implements a first-order filter algorithm by time division processing of a dividing time length corresponding to the filter order, and outputs output-data within each sampling period. - View Dependent Claims (2, 3, 4, 5)
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6. An effect applying apparatus comprising:
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a first memory which stores plural pieces of Finite Impulse Response (FIR) coefficient data used for implementing an FIR filter algorithm; and a processor which receives plural pieces of input data to be subjected to the FIR filter algorithm, the plural pieces of received input data being stored in a second memory, uses the plural pieces of FIR coefficient data stored in the first memory and the plural pieces of received input data stored in the second memory to multiply each piece of FIR coefficient data and each piece of input data together as many times as a number corresponding to a designated filter order, and sums up resultant products, wherein, when an acoustic effect is applied to an original tone by convoluting the original tone with impulse response data of an acoustic effect tone, the processor; implements the FIR filter algorithm to convolute the original tone with first half data of the impulse response data in the time domain of a unit of a sampling period; and further implements a Fast Fourier Transform (FFT) algorithm on second half data of the impulse response data in the frequency domain of a unit of a block, thereby convoluting the original tone with the second half data. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A method for implementing a filter algorithm under control of a processor of a signal processing apparatus, the signal processing apparatus comprising a first memory which stores plural pieces of coefficient data to be used for implementing the filter algorithm and containing plural coefficient data sets as many as a number corresponding to a filter order of the filter algorithm for at least one sort of filter algorithm of a variable filter order, and a second memory which stores input data sets from a last sample to a sample before the (filter-order-1)-th sample for every filter algorithm as delay data sets, the method comprising:
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receiving plural pieces of input data to be subjected to the filter algorithm; designating a filter order of the filter algorithm; implementing the filter algorithm using the plural pieces of coefficient data storing unit stored in the first memory and the plural pieces of received input data as many times as a number corresponding to the designated filter order, in which filter algorithm each piece of coefficient data and each piece of input data are multiplied together and resultant products are summed up, and outputting a result of implementing the filter algorithm, wherein the implementing the filter algorithm comprises successively receiving the coefficient data stored in the first memory and current input data stored in the second memory, repeatedly implementing a first-order filter algorithm by time division processing of a dividing time length corresponding to the filter order, and outputting output-data within each sampling period.
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14. A method for implementing a Finite Impulse Response (FIR) filter algorithm under control of a processor of an effect applying apparatus, the effect applying apparatus comprising a first memory which stores plural pieces of Finite Impulse Response (FIR) coefficient data used for implementing the FIR filter algorithm, and a second memory, and the method comprising:
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storing plural pieces of received input data to be subjected to the FIR filter algorithm in the second memory; and implementing the FIR filter algorithm using the plural pieces of FIR coefficient data stored in the first memory and the plural pieces of received input data stored in the second memory as many times as a number corresponding to a designated filter order, in which filter algorithm each piece of FIR coefficient data and each piece of input data are multiplied together and resultant products are summed up, wherein, when an acoustic effect is applied to an original tone by convoluting the original tone with impulse response data of an acoustic effect tone, the method further comprises; implementing the FIR filter algorithm to convolute the original tone with first half data of the impulse response data in the time domain of a unit of a sampling period; and implementing a Fast Fourier Transform algorithm on second half data of the impulse response data in the frequency domain of a unit of a block, thereby convoluting the original tone with the second half data. - View Dependent Claims (15)
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Specification