Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks

• US 10,339,982 B2
• Filed: 06/29/2016
• Issued: 07/02/2019
• Est. Priority Date: 05/09/2005
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: Bertin, Claude L., Huang, X. M. Henry, Rueckes, Thomas, Sivarajan, Ramesh
• Primary Examiner(s): Lam, David
• Application Number:
  US15/197,186
• Publication Number:
  US 20160314820A1
• Time in Patent Office: 1,098 Days
• Field of Search: 365148, 365 51, 365 63, 257 2- 5
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/16 Memory cell being a nanotube, e.g. suspended nanotube
• CPC Class Codes: G11C 2213/19 Memory cell comprising at least a nanowire and only two terminals
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 27/10 including a plurality of individual components in a repetitive configuration
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10K 10/50 : Bistable switching devices
• CPC Class Codes: H10K 85/221 : Carbon nanotubes
• CPC Class Codes: Y10S 977/943 : Information storage or retrieval using nanostructure

Abstract

Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.

Claims

1. A circuit for routing electrical signals, said circuit comprising:

a first plurality of wires;

a second plurality of wires; and

a plurality of nonvolatile nanotube block switches, wherein each nonvolatile nanotube block switch is in electrical communication with at least one wire of said first plurality of wires and at least one wire of said second plurality of wires, wherein each nonvolatile nanotube block switch is programmable to an on state and an off state, and wherein each nonvolatile nanotube block switch is dimensioned such that said on state has a resistance value suitable for electric signal flow between at least one wire of said first plurality of wires and at least one wire of said second plurality of wires.

2. The circuit of claim 1, wherein said resistance value for said on state is less than a resistance value for said off state.

3. The circuit of claim 1, wherein said resistance value for said on state is in a range of 50 to 100 Ohms.

4. The circuit of claim 1, wherein said resistance value for said on state is in a range of 100 to 1000 Ohms.

5. The circuit of claim 1, wherein said resistance value for said on state is in a range of 1 to 10 kiloOhms.

6. The circuit of claim 1, wherein said resistance value for said on state matches the characteristic impedance of said wires within said first plurality of wires.

7. The circuit of claim 6, wherein said first plurality of wires is a plurality of transmission lines.

8. The circuit of claim 1, wherein said resistance value for said on state matches the characteristic impedance of said wires within said second plurality of wires.

9. The circuit of claim 8, wherein said second plurality of wires is a plurality of transmission lines.

10. The circuit of claim 1, wherein said circuit for routing electrical signals is incorporated into a programmable logic device.

11. A circuit for routing electrical signals, said circuit comprising:

a first wire;

a first plurality of wires; and

a plurality of nonvolatile nanotube block switches, wherein each nonvolatile nanotube block switch is in electrical communication with said first wire and at least one wire of said first plurality of wires, wherein each nonvolatile nanotube block switch is programmable to an on state and an off state, and wherein each nonvolatile nanotube block switch is dimensioned such that said on state has a resistance value suitable for electric signal flow between said first wire and at least one wire of said first plurality of wires.

12. The circuit of claim 11, wherein said resistance value for said on state is less than a resistance value for said off state.

13. The circuit of claim 11, wherein said resistance value for said on state is in a range of 50 to 100 Ohms.

14. The circuit of claim 11, wherein said resistance value for said on state is in a range of 100 to 1000 Ohms.

15. The circuit of claim 11, wherein said resistance value for said on state is in a range of 1 to 10 kiloOhms.

16. The circuit of claim 11, wherein said resistance value for said on state matches the characteristic impedance of said first wire.

17. The circuit of claim 16, wherein said first wire is a transmission line.

18. The circuit of claim 11, wherein said resistance value for said on state matches the characteristic impedance of said wires within said first plurality of wires.

19. The circuit of claim 18, wherein said first plurality of wires is a plurality of transmission lines.

20. The circuit of claim 11, wherein said circuit for routing electrical signals is incorporated into a programmable logic device.

21. A method for routing electrical signals, comprising:

programming into an on state at least one nonvolatile nanotube block switch in a plurality of nonvolatile nanotube block switches by transmitting an electrical stimulus to said at least one nonvolatile nanotube block switch; and

transmitting electrical signals through at least one nonvolatile nanotube block switch in an on state in said plurality of nonvolatile nanotube block switches.

22. The method of claim 21, further comprising initially programming into an off state all nonvolatile nanotube block switches in said plurality of nonvolatile nanotube block switches.

23. The method of claim 21, further comprising programming into an off state at least one nonvolatile nanotube block switch in said plurality of nonvolatile nanotube block switches by transmitting an electrical stimulus to said at least one nanotube block switch.

24. The method of claim 23, wherein said on state corresponds with a logic 1 and said off state corresponds with a logic 0.

25. The method of claim 24, wherein said plurality of nonvolatile nanotube block switches are programmed into on states and off states in a combination that corresponds with a bit pattern.