Strobe acquisition and tracking
First Claim
Patent Images
1. A memory controller, comprising:
- an interface to receive a data strobe signal and corresponding read data, wherein the data strobe signal and the read data correspond to a read command issued by the memory controller, and wherein the read data is received in accordance with the data strobe signal;
a comparison circuit to determine a current timing offset between the data strobe signal and an internally generated data strobe enable signal, internally generated by the memory controller;
data receive circuitry, including gate logic to gate the data strobe signal with the internally generated data strobe signal to generate a clean data strobe signal, and data capture logic responsive to the clean data strobe signal to capture the read data; and
a circuit to dynamically determine a mode of operation of the memory controller in accordance with the determined current timing offset, wherein the mode of operation is selected from among a set of modes of operation that include a first mode of operation in which the memory controller synchronizes the internally generated data strobe enable signal with the received read data and data strobe signal, and a second mode of operation in which the memory controller maintains synchronization between the internally generated data strobe enable signal and the received read data and data strobe signal.
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Abstract
A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.
30 Citations
20 Claims
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1. A memory controller, comprising:
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an interface to receive a data strobe signal and corresponding read data, wherein the data strobe signal and the read data correspond to a read command issued by the memory controller, and wherein the read data is received in accordance with the data strobe signal; a comparison circuit to determine a current timing offset between the data strobe signal and an internally generated data strobe enable signal, internally generated by the memory controller; data receive circuitry, including gate logic to gate the data strobe signal with the internally generated data strobe signal to generate a clean data strobe signal, and data capture logic responsive to the clean data strobe signal to capture the read data; and a circuit to dynamically determine a mode of operation of the memory controller in accordance with the determined current timing offset, wherein the mode of operation is selected from among a set of modes of operation that include a first mode of operation in which the memory controller synchronizes the internally generated data strobe enable signal with the received read data and data strobe signal, and a second mode of operation in which the memory controller maintains synchronization between the internally generated data strobe enable signal and the received read data and data strobe signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of operating a memory controller, comprising:
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receiving, at an interface of the memory controller, a data strobe signal and corresponding read data, wherein the data strobe signal and the read data correspond to a read command issued by the memory controller, and wherein the read data is received in accordance with the data strobe signal; determining a current timing offset between the data strobe signal and an internally generated data strobe enable signal, internally generated by the memory controller; gating the data strobe signal with the internally generated data strobe signal to generate a clean data strobe signal; acquiring the read data using the clean data strobe signal; and dynamically determining a mode of operation of the memory controller in accordance with the determined current timing offset, wherein the mode of operation is selected from among a set of modes of operation that include a first mode of operation in which the memory controller synchronizes the internally generated data strobe enable signal with the received read data and data strobe signal, and a second mode of operation in which the memory controller maintains synchronization between the internally generated data strobe enable signal and the received read data and data strobe signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A memory controller, comprising:
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an interface to receive a data strobe signal and corresponding read data, wherein the data strobe signal and the read data correspond to a read command issued by the memory controller, and wherein the read data is received in accordance with the data strobe signal; a lock detection circuit to determine if synchronization between an internally generated data strobe enable signal of the memory controller and the received data strobe signal has been achieved, and to output a corresponding lock signal in accordance with the determination; and a circuit to dynamically determine a mode of operation of the memory controller in accordance with the lock signal, wherein the mode of operation is selected from among a set of modes of operation that include a first mode of operation in which the memory controller synchronizes the internally generated data strobe enable signal with the received read data and data strobe signal, and a second mode of operation in which the memory controller maintains synchronization between internally generated data strobe enable signal and the received read data and data strobe signal.
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Specification