Erase-verify method for three-dimensional memories and memory system

• US 10,340,017 B2
• Filed: 11/06/2017
• Issued: 07/02/2019
• Est. Priority Date: 11/06/2017
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Ku, Shaw-Hung, Huang, Yu-Hung, Cheng, Cheng-Hsien, Lee, Chih-Wei, Suzuki, Atsuhiro, Tsai, Wen-Jer
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US15/803,986
• Publication Number:
  US 20190139615A1
• Time in Patent Office: 603 Days
• Field of Search: 36518529, 365218
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.

Claims

1. An erase-verify method for a three-dimensional (3D) memory, the 3D memory including at least one memory cell string including a plurality of memory cells, the memory cells including a first group of memory cells and a second group of memory cells, each of the memory cells coupled to a word line, the erase-verify method comprising:

performing a first erase-verify operation on the first group of memory cells, wherein the first erase-verify operation comprises;

applying an erase-verify voltage to the word lines coupled to a first portion of the first group of memory cells and a first pass voltage to the word lines coupled to a second portion of the first group of memory cells in a first phase of the first erase-verify operation, the second portion of the first group of memory cells is different from the first portion of the first group of memory cells; and

after the first phase of the first erase-verify operation, applying the erase-verify voltage to the word lines coupled to the memory cells in the second portion of the first group of memory cells and the first pass voltage to the word lines coupled to the memory cells in the first portion of the first group of memory cells in a second phase of the first erase-verify operation; and

after performing the first erase-verify operation on the first group of memory cells, performing a second erase-verify operation on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully, wherein the second erase-verify operation comprises;

applying the erase-verify voltage to the word lines coupled to a first portion of the second group of memory cells and a second pass voltage to the word lines coupled to a second portion of the second group of memory cells in a first phase of the second erase-verify operation, the second portion of the second group of memory cells is different from the first portion of the second group of memory cells; and

after the first phase of the first erase-verify operation, applying the verify voltage to the word lines coupled to the second portion of the second group of memory cells and the second pass voltage to the word lines coupled to the first portion of the second group of memory cells in a second phase of the second erase-verify operation.

2. The erase-verify method according to claim 1, wherein the first group of memory cells is adjacent to one another, and the second group of memory cells is adjacent to one another.

3. The erase-verify method according to claim 1, wherein the first pass voltage is greater than the second pass voltage.

4. The erase-verify method according to claim 1, wherein the word lines includes interleaving even and odd word lines, the first portion of the first group of memory cells are connected to the odd word lines of the word lines coupled to the first group of memory cells, and the second portion of the first group of memory cells are connected to the even word lines of the word lines coupled to the first group of memory cells.

5. The erase-verify method according to claim 1, wherein the word lines includes interleaving even and odd word lines, the first portion of the second group of memory cells are connected to the odd word lines of the word lines coupled to the second group of memory cells, and the second portion of the second group of memory cells are connected to the even word lines of the word lines coupled to the second group of memory cells.

6. The erase-verify method according to claim 1, further comprising:

increasing an erase voltage in condition that the first group of memory cells is verified as erased unsuccessfully or the second group of memory cells is verified as erased unsuccessfully; and

applying the increased erase voltage to erase the at least one memory cell string.

7. A memory system, comprising:

a three dimensional (3D) memory, including at least one memory cell string extending vertically through layers of the 3D memory, the at least one memory cell string including a plurality of memory cells, the memory cells including a first group of memory cells and a second group of memory cells, each of the memory cells coupled to a word line; and

a controller, coupled to the 3D memory, for performing a first erase-verify operation on the first group of memory cells, wherein the first erase-verify operation comprises that the controller applies a erase-verify voltage to the word lines coupled to a first portion of the first group of memory cells and a first pass voltage to the word lines coupled to a second portion of the first group of memory cells in a first phase of the first erase-verify operation, and after the first phase of the first erase-verify operation, the controller applies the erase-verify voltage to the word lines coupled to the second portion of the first group of memory cells and the first pass erase-voltage to the word lines coupled to the first portion of the first group of memory cells in a second phase of the first erase-verify operation, wherein the second portion of the first group of memory cells is different from the first portion of the first group of memory cells;

and after performing the first erase-verify operation on the first group of memory cells, performing a second erase-verify operation on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully, wherein the second erase-verify operation comprises that the controller applies the erase-verify voltage to the word lines coupled to a first portion of the second group of memory cells and a second pass voltage to the word lines coupled to a second portion of the second group of memory cells in a first phase of the second erase-verify operation, and after the first phase of the first erase-verify operation, the controller applies the erase-verify voltage to the word lines coupled to the second portion of the second group of memory cells and the second pass voltage to the word lines coupled to the first portion of the second group of memory cells in a second phase of the second erase-verify operation, wherein the second portion of the second group of memory cells is different from the first portion of the second group of memory cells.

8. The memory system according to claim 7, wherein the first group of memory cells is adjacent to one another, and the second group of memory cells is adjacent to one another.

9. The memory system according to claim 7, wherein the first pass voltage is greater than the second pass voltage.

10. The memory system according to claim 7, wherein the word lines includes interleaving even and odd word lines, the first portion of the first group of memory cells is connected to the odd word lines of the word lines coupled to the first group of memory cells, and the second portion of the first group of memory cells is connected to the even word lines of the word lines coupled to the first group of memory cells.

11. The memory system according to claim 7, wherein the word lines includes interleaving even and odd word lines, the first portion of the second group of memory cells is connected to the odd word lines of the word lines coupled to the second group of memory cells, and the second portion of the second group of memory cells is connected to the even word lines of the word lines coupled to the second group of memory cells.

12. The memory system according to claim 7, wherein the controller further increases an erase voltage in condition that the first group of memory cells is verified as erased unsuccessfully or the second group of memory cells is verified as erased unsuccessfully and applies the increased erase voltage to erase the at least one memory cell string.