Strain relief epitaxial lift-off via pre-patterned mesas

• US 10,340,187 B2
• Filed: 03/18/2016
• Issued: 07/02/2019
• Est. Priority Date: 03/18/2015
• Status: Active Grant

• Current Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Forrest, Stephen R., Lee, Kyusang, Fan, Dejiu
• Primary Examiner(s): Ahmed, Shamim
• Application Number:
  US15/558,230
• Publication Number:
  US 20180047627A1
• Time in Patent Office: 1,201 Days
• CPC Class Codes: C09K 13/00 Etching, surface-brightening or pickling compositions for glass C03C15/00, C03C25/66; for mortars, concrete, artificial or natural stone or ceramics C04B41/5338 ; for metallic material C23F, C23G1/00, C25F1/00; for semi-conductors H01L
• CPC Class Codes: C30B 33/08 Etching
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 21/7813 leaving a reusable substrate, e.g. epitaxial lift off
• CPC Class Codes: H01L 31/1896 for thin-film semiconductors
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

Disclosed herein are methods to eliminate or reduce the peeling-off of epitaxial lifted-off thin film epilayers on secondary host substrates that allow for the fabrication of high yield ELO processed thin film devices. The methods employ patterned strain-relief trenches.

Claims

1. A method of fabricating a thin film device, comprising:

a. depositing a sacrificial layer over a growth substrate;

b. depositing an epilayer over the sacrificial layer;

c. depositing a photoresist layer over the epilayer;

d. patterning one or more trenches through the photoresist layer using photolithography, wherein the one or more trenches expose an area of the underlying epilayer;

e. depositing a metal layer over the epilayer;

f. removing the photoresist layer such that any portions of the metal layer overlying the photoresist layer are lifted off, exposing a different area of the underlying epilayer;

g. patterning one or more trenches through the exposed different area of the epilayer, wherein the one or more trenches expose an area of the underlying sacrificial layer or an area of the underlying growth substrate;

h. bonding the metal layer to a metal-coated host substrate; and

i. performing epitaxial lift off of the epilayer by etching the sacrificial layer.

2. The method of claim 1, wherein the one or more trenches of step g separate the epilayer into one or more rows.

3. The method of claim 1, wherein the one or more trenches of step g are configured to relieve the stress of the epilayer.

4. The method of claim 1, wherein the one or more trenches of step g are configured to reduce at least one of cracked epilayers, partial peel off of epilayers, and short-circuited devices after the epitaxial lift-off process.

5. The method of claim 1, wherein the epilayer has an area of at least 10,000 square microns.

6. The method of claim 5, wherein the area is in a range from about 1,000,000 square microns to about 100,000,000 square microns.

7. The method of claim 1, wherein the epilayer comprises at least one of Si and III-V semiconductors.

8. The method of claim 1, wherein the metal layer is bonded to the metal-coated host substrate by at least one of cold-weld bonding and van-der Waals bonding.

9. The method of claim 1, wherein the host substrate is chosen from a plastic substrate, a semiconductor substrate, and a metallic substrate.

10. The method of claim 1, wherein the one or more trenches of step g are 250 microns or less in width.

11. A method of fabricating a thin film device, comprising:

a. depositing a sacrificial layer over a growth substrate;

b. depositing an epilayer over the sacrificial layer;

c. depositing a metal layer over the epilayer;

d. depositing a photoresist layer over the epilayer;

e. patterning one or more trenches through the photoresist layer using photolithography, wherein the one or more trenches expose an area of the underlying metal layer;

f. patterning one or more trenches through the exposed area of the metal layer, wherein the one or more trenches expose an area of the underlying epilayer;

g. patterning one or more trenches through the exposed area of the epilayer, wherein the one or more trenches expose an area of the underlying sacrificial layer or an area of the underlying growth substrate;

h. removing the photoresist layer;

i. bonding the metal layer to a metal-coated host substrate; and

j. performing epitaxial lift off of the epilayer by etching the sacrificial layer.

12. The method of claim 11, wherein the one or more trenches of step g separate the epilayer into one or more rows.

13. The method of claim 11, wherein the one or more trenches of step g are configured to relieve the stress of the epilayer.

14. The method of claim 11, wherein the one or more trenches of step g are configured to reduce at least one of cracked epilayers, partial peel off of epilayers, and short-circuited devices after the epitaxial lift-off process.

15. The method of claim 11, wherein the epilayer has an area of at least 10,000 square microns.

16. The method of claim 15, wherein the area is in a range from about 1,000,000 square microns to about 100,000,000 square microns.

17. The method of claim 11, wherein the epilayer comprises at least one of Si and III-V semiconductors.

18. The method of claim 11, wherein the metal layer is bonded to the metal-coated host substrate by at least one of cold-weld bonding and van-der Waals bonding.

19. The method of claim 11, wherein the host substrate is chosen from a plastic substrate, a semiconductor substrate, and a metallic substrate.

20. The method of claim 11, wherein the one or more trenches of step g are 250 microns or less in width.