FinFET gate structure and method for fabricating the same

• US 10,340,192 B2
• Filed: 11/15/2017
• Issued: 07/02/2019
• Est. Priority Date: 10/28/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Jangjian, Shiu-Ko, Yu, Ren-Hau, Jeng, Chi-Cherng
• Primary Examiner(s): Le, Dung A.
• Application Number:
  US15/813,448
• Publication Number:
  US 20180076091A1
• Time in Patent Office: 594 Days
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure is fluorine incorporated and includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure is fluorine incorporated includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.

Claims

1. A semiconductor device, comprising:

a gate structure comprising;

a high-k dielectric layer;

a first metal layer over the high-k dielectric layer, wherein the first metal layer is a TiAl layer or a TaAl layer; and

a metal filler over the first metal layer, wherein;

a first surface of the first metal layer faces a gate spacer adjacent the gate structure,

a second surface of the first metal layer faces the metal filler,

a concentration of Al atoms at or near the first surface of the first metal layer is higher than a concentration of Al atoms in a region of the first metal layer between the first surface and the second surface, and

a concentration of Al atoms at or near the second surface of the first metal layer is higher than the concentration of Al atoms in the region of the first metal layer between the first surface and the second surface.

2. The semiconductor device of claim 1, comprising:

a second metal layer disposed between the metal filler and the first metal layer, and

a third metal layer disposed between the high-k dielectric layer and the first metal layer, wherein;

the second metal layer interfaces with the second surface, and

the third metal layer interfaces with the first surface.

3. The semiconductor device of claim 2, wherein the second metal layer and the third metal layer comprise titanium nitride.

4. The semiconductor device of claim 1, comprising:

a source/drain region; and

an etch stop layer, wherein the etch stop layer overlies the source/drain region and the gate spacer.

5. The semiconductor device of claim 4, wherein the etch stop layer contacts the source/drain region and the gate spacer.

6. The semiconductor device of claim 1, comprising:

a silicon oxide layer disposed between the high-k dielectric layer and a substrate underlying the high-k dielectric layer.

7. The semiconductor device of claim 1, wherein the high-k dielectric layer comprises fluorine.

8. The semiconductor device of claim 1, comprising:

a second metal layer between the high-k dielectric layer and the first metal layer.

9. The semiconductor device of claim 8, comprising:

a third metal layer between the second metal layer and the first metal layer.

10. The semiconductor device of claim 9, wherein the second metal layer comprises titanium nitride and the third metal layer comprises tantalum nitride.

11. The semiconductor device of claim 9, comprising:

a fourth metal layer between the third metal layer and the first metal layer.

12. The semiconductor device of claim 11, wherein the second metal layer comprises titanium nitride, the third metal layer comprises tantalum nitride, and the fourth metal layer comprises titanium nitride.

13. A semiconductor device, comprising:

a gate structure comprising;

a high-k dielectric layer;

a stacked structure comprising a plurality of metal layers over the high-k dielectric layer; and

a metal filler in contact with a side wall and a bottom region of the stacked structure, wherein;

the side wall has a fluorine concentration substantially from 5 atomic percent to 20 atomic percent, and

the bottom region has a fluorine concentration substantially from 1 atomic percent to 15 atomic percent.

14. The semiconductor device of claim 13, wherein:

a first metal layer of the plurality of metal layers is a TiAl layer or a TaAl layer,

a first surface of the first metal layer faces a gate spacer adjacent the gate structure,

a second surface of the first metal layer faces the metal filler, and

a concentration of Al atoms at or near the first surface of the first metal layer is higher than a concentration of Al atoms in a region of the first metal layer between the first surface and the second surface.

15. The semiconductor device of claim 14, wherein a concentration of Al atoms at or near the second surface of the first metal layer is higher than a concentration of Al atoms in the region of the first metal layer between the first surface and the second surface.

16. The semiconductor device of claim 13, comprising:

a semiconductor fin disposed under the gate structure.

19. The semiconductor device of claim 13, wherein:

a first metal layer of the plurality of metal layers comprises Al,

a concentration of Al atoms in a first region of the first metal layer is different than the concentration of Al atoms in a second region of the first metal layer.

20. The semiconductor device of claim 13, wherein:

a first metal layer of the plurality of metal layers comprises Al,

a first surface of the first metal layer faces a gate spacer adjacent the gate structure,

a second surface of the first metal layer faces the metal filler,

a concentration of Al atoms at or near the first surface of the first metal layer is higher than a concentration of Al atoms in a region of the first metal layer between the first surface and the second surface, and

a concentration of Al atoms at or near the second surface of the first metal layer is higher than the concentration of Al atoms in the region of the first metal layer between the first surface and the second surface.

17. A semiconductor device, comprising:

a gate structure comprising;

a high-k dielectric layer;

a first metal layer over the high-k dielectric layer, wherein the first metal layer comprises Al; and

a metal filler over the first metal layer, wherein;

a first surface of the first metal layer faces a gate spacer adjacent the gate structure,

a second surface of the first metal layer faces the metal filler,

a concentration of Al atoms at or near the first surface of the first metal layer is higher than a concentration of Al atoms in a region of the first metal layer between the first surface and the second surface, and

a concentration of Al atoms at or near the second surface of the first metal layer is higher than the concentration of Al atoms in the region of the first metal layer between the first surface and the second surface.

18. The semiconductor device of claim 17, comprising a stacked structure comprising a plurality of metal layers over the high-k dielectric layer, wherein:

the first metal layer is one of the plurality of metal layers,

a metal filler is in contact with a side wall and a bottom region of the stacked structure,

the side wall has a fluorine concentration substantially from 5 atomic percent to 20 atomic percent, and

the bottom region has a fluorine concentration substantially from 1 atomic percent to 15 atomic percent.