Method of manufacturing semiconductor structure comprising plurality of through holes using metal hard mask

• US 10,340,218 B2
• Filed: 10/11/2017
• Issued: 07/02/2019
• Est. Priority Date: 11/17/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yu-Hung, Huang, Chun-Hsien, Chen, I-Tseng
• Primary Examiner(s): Le, Dung A.
• Application Number:
  US15/729,816
• Publication Number:
  US 20180047666A1
• Time in Patent Office: 629 Days
• Field of Search: None
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method of manufacturing a semiconductor structure including a conductive structure, a dielectric layer, and a plurality of conductive features is disclosed. The dielectric layer is formed on the conductive structure. A plurality of through holes is formed in the dielectric layer using a metal hard mask, and at least one of the through holes exposes the conductive structure. The conductive features are formed in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees.

Claims

1. A method for manufacturing a semiconductor structure comprising:

forming a first portion of a dielectric layer to conceal a conductive structure;

removing some of the first portion of the dielectric layer to expose a top surface of the conductive structure, wherein a top of the first portion of the dielectric layer is at or above the top surface of the conductive structure after removing some of the first portion of the dielectric layer;

forming a second portion of the dielectric layer over the first portion of the dielectric layer and over the top surface of the conductive structure;

forming a metal hard mask over the dielectric layer;

patterning the metal hard mask to form a patterned metal hard mask;

patterning the first portion of the dielectric layer and the second portion of the dielectric layer with the patterned metal hard mask to define a first through hole extending through the first portion of the dielectric layer and the second portion of the dielectric layer; and

patterning the second portion of the dielectric layer with the patterned metal hard mask to define a second through hole extending through the second portion of the dielectric layer.

2. The method of claim 1, wherein:

the conductive structure comprises a source/drain feature and a gate structure, and

removing some of the first portion of the dielectric layer to expose the top surface of the conductive structure comprises;

exposing a top surface of the gate structure.

3. The method of claim 2, wherein the source/drain feature remains concealed by the dielectric layer after removing some of the first portion of the dielectric layer to expose the top surface of the conductive structure.

4. The method of claim 1, wherein:

the conductive structure comprises a source/drain feature and a gate structure, and

patterning the metal hard mask comprises;

forming a first opening in the metal hard mask over the source/drain feature and forming a second opening in the metal hard mask over the gate structure.

5. The method of claim 4, wherein:

patterning the first portion of the dielectric layer and the second portion of the dielectric layer with the patterned metal hard mask to define the first through hole extending through the first portion of the dielectric layer and the second portion of the dielectric layer comprises;

patterning the first portion of the dielectric layer and the second portion of the dielectric layer through the first opening in the metal hard mask; and

patterning the second portion of the dielectric layer with the patterned metal hard mask to define the second through hole extending through the second portion of the dielectric layer comprises;

patterning the second portion of the dielectric layer through the second opening in the metal hard mask.

6. The method of claim 1, wherein:

the conductive structure comprises a silicide contact, and

patterning the first portion of the dielectric layer and the second portion of the dielectric layer with the patterned metal hard mask to define a first through hole extending through the first portion of the dielectric layer and the second portion of the dielectric layer, comprises;

exposing the silicide contact through the first through hole.

7. The method of claim 1, wherein the second through hole extends merely through the second portion of the dielectric layer.

8. The method of claim 1, wherein a material composition of the first portion of the dielectric layer is different than a material composition of the second portion of the dielectric layer.

9. The method of claim 1, comprising:

forming a first conductive feature in the first through hole and a second conductive feature in the second through hole.

10. A method for manufacturing a semiconductor structure comprising:

forming a first portion of a dielectric layer over a first portion of a conductive structure;

forming a second portion of the dielectric layer over an exposed, second portion of the conductive structure and over the first portion of the dielectric layer;

forming a metal hard mask over the dielectric layer;

patterning the metal hard mask to form a patterned metal hard mask;

patterning the first portion of the dielectric layer and the second portion of the dielectric layer with the patterned metal hard mask to define a first through hole extending through the first portion of the dielectric layer and the second portion of the dielectric layer; and

patterning the second portion of the dielectric layer with the patterned metal hard mask to define a second through hole extending through the second portion of the dielectric layer.

11. The method of claim 10, wherein forming the second portion of the dielectric layer comprises:

forming the second portion of the dielectric layer to contact the second portion of the conductive structure.

12. The method of claim 10, wherein a material composition of the first portion of the dielectric layer is different than a material composition of the second portion of the dielectric layer.

13. The method of claim 10, wherein the first portion of the conductive structure is a source/drain feature and the second portion of the conductive structure is a gate structure.

14. The method of claim 10, comprising:

forming a first conductive feature in the first through hole and a second conductive feature in the second through hole.