Circuit substrate and method for manufacturing circuit substrate

• US 10,340,243 B2
• Filed: 06/11/2018
• Issued: 07/02/2019
• Est. Priority Date: 02/03/2016
• Status: Active Grant

• Current Assignee: Fujifilm Business Innovation Corp. (Fujifilm Holdings Corporation)
• Original Assignee: Fuji Xerox Company Limited (Xerox Holdings Corp.)
• Inventors: Iguchi, Daisuke, Hattori, Atsunori
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US16/004,486
• Publication Number:
  US 20180294240A1
• Time in Patent Office: 386 Days
• Field of Search: 257737
• CPC Class Codes: H01L 21/4875 Connection or disconnection of other leads to or from bases or plates
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/492 Bases or plates or solder therefor
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate

Abstract

A circuit substrate includes: a base material; and a capacitor layer. The capacitor layer includes a first metal layer that is provided on the base material, a dielectric layer that is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer. The first metal layer includes a first electrode region which is provided on the base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected. The second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected.

Claims

1. A circuit substrate comprising:

a base material; and

a capacitor layer including;

a first metal layer on the base material;

a dielectric layer on the first metal layer; and

a second metal layer on the dielectric layer,

wherein the first metal layer includes a first electrode region on the base material, which is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit through the capacitor layer is to be connected, and

wherein the second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is to be connected.

2. The circuit substrate according to claim 1,

wherein the first metal layer includes a projection portion projecting from a height position of a lower surface of the dielectric layer toward the first electrode region, and

wherein the circuit substrate is configured without any interfaces between the first metal layer and the projection portion.

3. The circuit substrate according to claim 1,

wherein the first electrode region is exposed at a height position of an upper surface of the dielectric layer or at a position lower than the height position of the upper surface of the dielectric layer.

4. The circuit substrate according to claim 1,

wherein the first electrode region is exposed at a height position of an upper surface of the dielectric layer.

5. The circuit substrate according to claim 1,

wherein the first electrode region is exposed at a height position of a lower surface of the dielectric layer or at a position lower than the height position of the lower surface of the dielectric layer.

6. The circuit substrate according to claim 5,

wherein the first electrode region is exposed at the height position of the lower surface of the dielectric layer.

7. The circuit substrate according to claim 1,

wherein the second electrode region is exposed at a position higher than a height position of an upper surface of the dielectric layer.

8. The circuit substrate according to claim 1,

wherein the first metal layer includes a third electrode region which is exposed from the dielectric layer and to which one of a terminal for a power supply potential and a terminal for a standard potential that are included in the circuit is connected, and

wherein the second metal layer includes a fourth electrode region in which the second metal layer is exposed and to which other of the terminal for a power supply potential and the terminal for a standard potential is connected.

9. The circuit substrate according to claim 8,

wherein the capacitor element is connected to the first electrode region and the second electrode region, and

wherein a semiconductor integrated circuit as the circuit is connected to the third electrode region and the fourth electrode region.

10. The circuit substrate according to claim 8, further comprising:

a first conductive portion for connecting the first metal layer to one of an external power supply potential and a standard potential which is extended from a vicinity of the first electrode region toward an inner layer side of the base material;

a second conductive portion for connecting the second metal layer to other of the external power supply potential and the standard potential which is extended from a vicinity of the second electrode region toward the inner layer side of the base material;

a third conductive portion for connecting the first metal layer to one of the external power supply potential and the standard potential which is extended from a vicinity of the third electrode region toward the inner layer side of the base material; and

a fourth conductive portion for connecting the second metal layer to other of the external power supply potential and the standard potential which is extended from a vicinity of the fourth electrode region toward the inner layer side of the base material.

11. The circuit substrate according to claim 10,

wherein, in a case where the base material is viewed through from one surface side, at least one conductive portion among the first to fourth conductive portions is connected to the first metal layer or the second metal layer in a position which overlaps a corresponding electrode region.

12. The circuit substrate according to claim 10,

wherein in a case where the base material is viewed through from one surface side, the first to the fourth conductive portions are connected to the first metal layer and the second metal layer respectively, in a position which overlaps a corresponding electrode region.

13. The circuit substrate according to claim 1,

wherein the first metal layer includes a third electrode region which is exposed from the dielectric layer and to which one of a terminal for power supply potential and a terminal for a standard potential which are included in the circuit is connected,

wherein the second metal layer includes a fourth electrode region in which the second metal layer is exposed and to which other of the terminal for a power supply potential and the terminal for a standard potential is connected,

wherein the third electrode region is exposed at a position higher than a height position of an upper surface of the dielectric layer, and

wherein the first metal layer and the third electrode region are connected to each other through a conductive portion which passes through the first metal layer and the dielectric layer and does not have an interface.

14. The circuit substrate according to claim 8,

wherein the base material includes a plurality of electrode regions at a front surface side including the third and the fourth electrode regions, and a plurality of electrode regions at a back surface side which are electrically connected to the plurality of electrode regions at the front surface side, respectively, through an inner portion of the base material, and

wherein a distance between the plurality of electrode regions at the front surface side is equal to a distance between the plurality of electrode regions at the back surface side.

15. The circuit substrate according to claim 8,

wherein the base material includes a plurality of electrode regions at a front surface side including the third and the fourth electrode regions, and a plurality of electrode regions at a back surface side which are electrically connected to the plurality of electrode regions at the front surface side, respectively, through an inner portion of the base material, and

wherein each of the plurality of electrode regions at the front surface side to which the circuit is connected and the plurality of electrode regions at the back surface side corresponding to each electrode regions are provided on an overlapping position in a case where the base material is viewed through from one surface side.

16. The circuit substrate according to claim 1, wherein, in a direction from the base material to the circuit, the first metal layer is both in direct contact with a face of the dielectric layer facing away from the circuit and also in direct contact with a face of the dielectric layer facing towards the circuit.

17. The circuit substrate according to claim 1, wherein, in a direction from the base material to the circuit, the first metal layer and the second metal layer connect to the circuit at positions equal in distance from the base material.

18. The circuit substrate according to claim 1, wherein each of the capacitor element and circuit is positioned further away from the base material than each of the first metal layer, dielectric layer, second metal layer, first electrode region and second electrode region.

19. The circuit substrate according to claim 1,

wherein the second electrode region is configured to directly contact the second terminal of the capacitor element.

20. The circuit substrate according to claim 1,

wherein a solder resist is formed on the second metal layer and the second electrode region is exposed from the solder resist.