Semiconductor devices including control logic levels, and related memory devices, control logic assemblies, electronic systems, and methods

• US 10,340,267 B1
• Filed: 12/29/2017
• Issued: 07/02/2019
• Est. Priority Date: 12/29/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sills, Scott E., Beigel, Kurt D.
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/858,229
• Publication Number:
  US 20190206862A1
• Time in Patent Office: 550 Days
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H03K 19/0948 : using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/20 : characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors

Abstract

A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting transistors laterally displaced from one another. A memory device, a thin film transistor control logic assembly, an electronic system, and a method of operating a semiconductor device are also described.

Claims

1. A semiconductor device, comprising:

a stack structure comprising decks each comprising;

a memory element level comprising memory elements; and

a control logic level in electrical communication with the memory element level and comprising control logic devices, at least one of the control logic devices of the control logic level of one or more of the decks comprising at least one device exhibiting transistors laterally displaced from one another.

2. The semiconductor device of claim 1, further comprising a base control logic structure in electrical communication with the stack structure and comprising additional control logic devices.

3. The semiconductor device of claim 2, wherein the additional control logic devices of the base control logic structure exhibit different configurations and have different operational functions than the control logic devices of the control logic level of each of the decks of the stack structure.

4. The semiconductor device of claim 1, further comprising an access device level comprising access devices electrically connected to the memory elements of the memory element level, the control logic level in electrical communication with the access device level.

5. The semiconductor device of claim 1, wherein the memory element level further comprises access devices electrically connected to the memory elements.

6. The semiconductor device of claim 1, wherein the at least one device comprises at least one circuit comprising:

a first transistor comprising a P-type source region, a P-type drain region, an N-type channel region between the P-type source region and the P-type drain region, and at least one gate electrode adjacent the N-type channel region; and

a second transistor laterally displaced from the first transistor and comprising an N-type source region, an N-type drain region, a P-type channel region between the N-type source region and the N-type drain region, and at least one additional gate electrode adjacent the P-type channel region.

7. The semiconductor device of claim 6, wherein:

the first transistor comprises a first vertical transistor comprising the P-type source region, the P-type drain region, the N-type channel region vertically between the P-type source region and the P-type drain region, and the at least one gate electrode laterally adjacent the N-type channel region; and

the second transistor comprises a second vertical transistor comprising the N-type source region, the N-type drain region, the P-type channel region vertically between the N-type source region and the N-type drain region, and the at least one additional gate electrode laterally adjacent the P-type channel region.

8. The semiconductor device of claim 7, wherein:

the first vertical transistor exhibits a first double-gate configuration comprising gate electrodes laterally adjacent opposing sides of the N-type channel region thereof; and

the second vertical transistor exhibits a second double-gate configuration comprising additional gate electrodes laterally adjacent opposing sides of the P-type channel region thereof.

9. The semiconductor device of claim 7, wherein:

the first vertical transistor exhibits a first single-gate configuration comprising only one gate electrode laterally adjacent the N-type channel region thereof; and

the second vertical transistor exhibits a second single-gate configuration comprising only one other gate electrode laterally adjacent the P-type channel region thereof.

10. The semiconductor device of claim 7, wherein:

the first vertical transistor exhibits a first gate-all-around configuration comprising a gate electrode substantially surrounding all sides of the N-type channel region thereof; and

the second vertical transistor exhibits a second gate-all-around configuration comprising another gate electrode substantially surrounding all sides of the P-type channel region thereof.

11. The semiconductor device of claim 7, wherein:

the N-type channel region of the first vertical transistor comprises a solid N-type conductivity material substantially filling the entire volume of the N-type channel region; and

the P-type channel region of the second vertical transistor comprises a solid P-type conductivity material substantially filling the entire volume of the P-type channel region.

12. The semiconductor device of claim 7, wherein:

the N-type channel region of the first vertical transistor exhibits an opening extending into an N-type conductivity material thereof; and

the P-type channel region of the second vertical transistor exhibits another opening extending into a P-type conductivity material thereof.

13. The semiconductor device of claim 6, wherein:

the first transistor comprises a first horizontal transistor comprising the P-type source region, the P-type drain region, the N-type channel region laterally between the P-type source region and the P-type drain region, and a gate electrode vertically adjacent the N-type channel region; and

the second transistor comprises a second horizontal transistor comprising the N-type source region, the N-type drain region, the P-type channel region laterally between the N-type source region and the N-type drain region, and an additional gate electrode vertically adjacent the P-type channel region.

14. The semiconductor device of claim 13, wherein:

the first horizontal transistor exhibits a first top-gate configuration comprising the gate electrode vertically overlying the N-type channel region thereof; and

the second horizontal transistor exhibits a second top-gate configuration comprising the additional gate electrode vertically overlying the P-type channel region thereof.

15. The semiconductor device of claim 13, wherein:

the first horizontal transistor exhibits a first bottom-gate configuration comprising the gate electrode vertically underlying the N-type channel region thereof; and

the second horizontal transistor exhibits a second bottom-gate configuration comprising another gate electrode vertically underlying the P-type channel region thereof.

16. The semiconductor device of claim 13, wherein:

upper surfaces of the P-type source region, the P-type drain region, the N-type channel region of the first horizontal transistor are substantially coplanar with one another; and

upper surfaces of the N-type source region, the N-type drain region, the P-type channel region of the second horizontal transistor are substantially coplanar with one another.

17. The semiconductor device of claim 13, wherein:

upper surfaces of two or more of the P-type source region, the P-type drain region, the N-type channel region of the first horizontal transistor are offset from one another; and

upper surfaces of two of more of the N-type source region, the N-type drain region, the P-type channel region of the second horizontal transistor are offset from one another.

18. The semiconductor device of claim 6, wherein:

the first transistor comprises a first FinFET comprising the P-type source region, the P-type drain region, the N-type channel region laterally between the P-type source region and the P-type drain region, and a gate electrode extending over the N-type channel region; and

the second transistor comprises a second FinFET comprising the N-type source region, the N-type drain region, the P-type channel region laterally between the N-type source region and the N-type drain region, and an additional gate electrode extending over the P-type channel region.

19. The semiconductor device of claim 18, wherein:

the gate electrode extends over opposing side surfaces and an upper surface of the N-type channel region of the first FinFET; and

the additional gate electrode extends over opposing side surfaces and an upper surface of the P-type channel region of the second FinFET.

20. The semiconductor device of claim 18, wherein:

the gate electrode substantially surrounds all surfaces of the N-type channel region of the first FinFET not covered by the P-type source region and the P-type drain region; and

the additional gate electrode substantially surrounds all surfaces of the P-type channel region of the second FinFET not covered by the N-type source region and the N-type drain region.

21. A memory device, comprising:

a base control logic structure comprising control logic devices; and

a stack structure in electrical communication with the base control logic structure and comprising decks each comprising;

a memory element level comprising memory elements; and

a control logic level in electrical communication with the memory element level and comprising additional control logic devices selected from the group comprising decoders, sense amplifiers, word line drivers, repair devices, memory test devices, multiplexers, error checking and correction devices, and self-refresh/wear leveling devices, at least one of the additional control logic devices comprising a circuit comprising neighboring, laterally displaced transistors having different channel conductivities than one another.

22. The memory device of claim 21, wherein control logic devices of the base control logic structure comprise one or more of charge pumps, delay-locked loop devices, and drain supply voltage regulators.

23. The memory device of claim 21, wherein the control logic level of each of the decks individually comprises the circuit.

24. The memory device of claim 21, wherein the control logic level of each of the decks of the stack structure exhibits substantially the same configuration as the control logic level of each other of the decks of the stack structure.

25. The memory device of claim 21, wherein the neighboring, laterally displaced transistors of the circuit comprise vertical transistors.

26. The memory device of claim 21, wherein the neighboring, laterally displaced transistors of the circuit comprise horizontal transistors.

27. The memory device of claim 21, wherein the neighboring, laterally displaced transistors of the circuit comprise fin field-effect transistors.

28. The memory device of claim 21, further comprising an access device level comprising access devices electrically connected to the memory elements of the memory element level, the control logic level in electrical communication with the access device level.

29. A thin film transistor control logic assembly comprising control logic devices selected from the group comprising decoders, sense amplifiers, word line drivers, repair devices, memory test devices, multiplexers, error checking and correction devices, and self-refresh/wear leveling devices, at least one of the control logic devices comprising at least one device exhibiting a transistor having an N-type channel region laterally displaced from another transistor having a P-type channel region.

30. A method of operating a semiconductor device, comprising:

controlling functions of a stack structure having multiple decks each comprising memory cells using control logic levels of the multiple decks, the control logic levels each comprising at least one control logic device exhibiting laterally-displaced transistors; and

controlling additional functions of the stack structure using a base control logic structure in electrical communication with the control logic levels of the stack structure.

31. An electronic system, comprising:

a semiconductor device comprising;

a stack structure comprising decks each comprising;

a memory element level comprising memory elements; and

a control logic level in electrical communication with the memory element level and comprising control logic devices, at least one of the control logic devices of the control logic level of one or more of the decks comprising at least one device exhibiting laterally-displaced transistors.