Method of maintaining the state of semiconductor memory having electrically floating body transistor

• US 10,340,276 B2
• Filed: 11/27/2018
• Issued: 07/02/2019
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US16/200,997
• Publication Number:
  US 20190096889A1
• Time in Patent Office: 217 Days
• CPC Class Codes: G11C 11/04 using storage elements having cylindrical form, e.g. rod, wire G11C11/12, G11C11/14 take precedence
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/772 : Field effect transistors
• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7855 : with at least two independent gates
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

Claims

1. An integrated circuit comprising:

an array of semiconductor memory cells formed in a semiconductor substrate having at least one surface, the array comprising;

said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;

a transistor comprising a source region, a floating body region, a drain region, and a gate;

a first bipolar device having a first floating base region, a first emitter, and a first collector; and

a second bipolar device having a second floating base region, a second emitter, and a second collector;

wherein said first floating base region and said second floating base region are common to said floating body region;

wherein said first collector is common to said second collector;

wherein application of back bias to said first and second collectors results in at least two stable floating base region charge levels;

wherein said transistor is usable to access said memory cell;

a first control circuit configured to apply said back bias to said first and second collectors; and

a second control circuit configured to access a selected memory cell selected from said semiconductor memory cells and perform a read or write operation on said selected memory cell.

2. The integrated circuit of claim 1, wherein said first control circuit is configured to provide electrical signals to at least two of said memory cells to maintain states of said at least two memory cells.

3. The integrated circuit of claim 2, wherein said electrical signals are constant voltage biases.

4. The integrated circuit of claim 2, wherein said electrical signals are periodic pulses of voltage.

5. The integrated circuit of claim 2, wherein said electrical signals result in at least two stable states.

6. The integrated circuit of claim 1, wherein said integrated circuit comprises a fin structure extending from said substrate.

7. The integrated circuit of claim 1, wherein said first control circuit comprises a voltage generator circuit.

8. The integrated circuit of claim 7, further comprising a multiplexer electrically connected between said voltage generator circuit and said first and second collectors.

9. The integrated circuit of claim 1, wherein said second control circuit comprises a reference generator circuit configured to sense potential of said floating body region.

10. The integrated circuit of claim 1, wherein said second control circuit comprises a read circuit connected to one of said source or drain region.

11. The integrated circuit of claim 10, further comprising a reference generator circuit connected to said read circuit.

12. An integrated circuit comprising:

an array of semiconductor memory cells formed in a semiconductor substrate having at least one surface, the array comprising;

said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;

a transistor comprising a source region, a floating body region, a drain region, and a gate;

a first bipolar device having a first floating base region, a first emitter, and a first collector; and

a second bipolar device having a second floating base region, a second emitter, and a second collector;

wherein said first floating base region and said second floating base region are common to said floating body region;

wherein said first collector is common to said second collector;

wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell;

wherein said state of said memory cell is maintained upon repeated read operations;

wherein said transistor is usable to access said memory cell;

a first control circuit configured to access a selected memory cell selected from said memory cells and perform a read or write operation on said selected memory cell; and

a second control circuit configured to provide electrical signals to perform a holding operation on said array, wherein said electrical signals are applied to a terminal not used for memory address selection.

13. The integrated circuit of claim 12, wherein said electrical signals to perform a holding operation are applied to a terminal connected to said first and second collectors.

14. The integrated circuit of claim 12, wherein said electrical signals to perform a holding operation are constant voltage biases.

15. The integrated circuit of claim 12, wherein said electrical signals to perform a holding operation are periodic pulses of voltage.

16. The integrated circuit of claim 12, wherein said electrical signals to perform a holding operation result in at least two stable states.

17. The integrated circuit of claim 12, wherein said integrated circuit comprises a fin structure extending from said substrate.

18. The integrated circuit of claim 12, wherein said first control circuit comprises a voltage generator circuit.

19. The integrated circuit of claim 18, further comprising a multiplexer electrically connected between said voltage generator circuit and said first and second collectors.

20. The integrated circuit of claim 12, wherein said second control circuit comprises a reference generator circuit configured to sense potential of said floating body region.

21. The integrated circuit of claim 12, wherein said second control circuit comprises a read circuit connected to one of said source or drain region.

22. The integrated circuit of claim 21, further comprising a reference generator circuit connected to said read circuit.