Method and apparatus for backside illumination sensor

• US 10,340,303 B2
• Filed: 03/15/2018
• Issued: 07/02/2019
• Est. Priority Date: 05/08/2017
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation), Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: Qi, Dekui, Chen, Fucheng
• Primary Examiner(s): Le, Dung A.
• Application Number:
  US15/922,514
• Publication Number:
  US 20180323226A1
• Time in Patent Office: 474 Days
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/3213 Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14645 Colour imagers

Abstract

A semiconductor device includes a device substrate having a dielectric layer and a metal wire in the dielectric layer, a first opening on the metal wire and having a bottom at a depth the same as an upper surface of the metal wire, a first insulation layer including a first color filter material on sidewalls of the first opening, a second opening disposed at opposite ends of the semiconductor device and having a bottom at a depth the same as the depth of the bottom of the first opening, and a second insulation layer including a second color filter material on sidewalls of the second opening. The first opening is for leading out the metal wire to a pad. The second opening is disposed along scribe lines. The semiconductor device simplifies the process of drawing out and isolating the pads and satisfies technical requirements of a back seal ring.

Claims

1. A semiconductor device, comprising;

a device substrate including a dielectric layer and a metal wire in the dielectric layer;

a first opening over the metal wire, the first opening having a bottom at a depth the same as an upper surface of the metal wire; and

a first insulation layer including a first color filter material on sidewalls of the first opening.

2. The semiconductor device of claim 1, further comprising:

a second opening disposed at opposite ends of the semiconductor device and having a bottom at a depth the same as the depth of the bottom of the first opening; and

a second insulation layer including a second color filter material on sidewalls of the second opening.

3. The semiconductor device of claim 2, further comprising:

a pixel region on the device substrate, the pixel region comprising a plurality of pixel units including a third color filler material, the pixel units being separated from each other by a metal grid; and

a microlens on each of the plurality of pixel units.

4. The semiconductor device of claim 3, wherein the metal grid comprises aluminum or tungsten.

5. The semiconductor device of claim 2, wherein the first color filter material and the second color filter material each comprise a same color filter material or different color filter materials.

6. The semiconductor device of claim 2, wherein the depth of the first opening and the depth of the second opening each are less than or equal to 3 microns;

and

the first opening has a width greater than or equal to 40 microns.

7. The semiconductor device of claim 1, further comprising:

a carrier substrate configured to carry the device substrate.

8. A method for manufacturing a semiconductor device, the method comprising:

providing a device substrate including a dielectric layer and a metal wire in the dielectric layer;

forming a first opening having a bottom at a depth the same as an upper surface of the metal wire; and

forming a first insulation layer including a first color filter material on sidewalls of the first opening.

9. The method of claim 8, further comprising:

forming a second opening disposed at opposite ends of the semiconductor device and having a bottom at a depth the same as the depth of the bottom of the first opening; and

forming a second insulation layer including a second color filter material on sidewalls of the second opening.

10. The method of claim 9, further comprising:

forming a patterned metal grid having a plurality of openings on the device substrate;

forming an oxide layer on the patterned metal grid filling the plurality of openings;

removing a portion of the oxide layer in the openings to form a plurality of gaps; and

filling the plurality of gaps with a third color filter material.

11. The method of claim 10, further comprising, after forming the oxide layer and prior to removing the portion of the oxide layer in the openings:

planarizing the oxide layer.

12. The method of claim 10, wherein the patterned metal grid comprises aluminum or tungsten.

13. The method of claim 9, wherein the first insulation layer and the second insulation layer each are formed by a lithography and etching process of the first color filter material and the second color filter material, respectively.

14. The method of claim 9, wherein the first color filter material and the second color filter material each comprise a same color filter material or different color filter materials.

15. The method of claim 14, wherein the different color filter materials comprise a red color filter material, a yellow color filter material, and a green color filter material.

16. The method of claim 9, wherein the depth of the first opening and the depth of the second opening each are less than or equal to 3 microns;

and

the first opening has a width greater than or equal to 40 microns.

17. The method of claim 9, further comprising:

forming a carrier layer below the device substrate.