Semiconductor device and method for manufacturing the same

• US 10,340,343 B2
• Filed: 01/04/2018
• Issued: 07/02/2019
• Est. Priority Date: 10/31/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lo, Wen-Shun, Chang, Yu-Chi, Tsui, Felix Ying-Kit
• Primary Examiner(s): Shook, Daniel P
• Application Number:
  US15/862,489
• Publication Number:
  US 20190131401A1
• Time in Patent Office: 544 Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor device includes a semiconductor substrate, a gate electrode, a pair of source/drain regions and a a threshold voltage adjusting region. The gate electrode is over the semiconductor substrate. The channel region is between the semiconductor substrate and the gate electrode. The source/drain regions are adjacent to two opposing sides of the channel region in a channel length direction. The threshold voltage adjusting region is adjacent to two opposing sides of the channel region in a channel width direction, wherein the threshold voltage adjusting region and the channel region have the same doping type.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a gate electrode over the semiconductor substrate;

a channel region between the semiconductor substrate and the gate electrode;

a pair of source/drain regions adjacent to two opposing sides of the channel region in a channel length direction; and

a threshold voltage adjusting region adjacent to two opposing sides of the channel region in a channel width direction, wherein the threshold voltage adjusting region and the channel region have the same doping type, and a depth of the threshold voltage adjusting region is greater than a depth of the pair of source/drain regions.

2. The semiconductor device of claim 1, further comprising an isolation structure in the semiconductor substrate.

3. The semiconductor device of claim 2, wherein the isolation structure comprises a shallow trench isolation (STI) in a trench of the semiconductor substrate.

4. The semiconductor device of claim 3, wherein the threshold voltage adjusting region is in a sidewall of the STI.

5. The semiconductor device of claim 1, wherein a doping concentration of the threshold voltage adjusting region is higher than a doping concentration of the channel region.

6. The semiconductor device of claim 5, wherein a ratio of the doping concentration of the threshold voltage adjusting region to the doping concentration of the channel region is substantially in a range from about 1.1 to about 2.0.

7. The semiconductor device of claim 5, wherein the channel region includes an edge region proximal to the threshold voltage adjusting region, and a central region distal to the threshold voltage adjusting region, and a first threshold voltage at the edge region is higher than a second threshold voltage of in the central region.

8. The semiconductor device of claim 7, wherein a ratio of the first threshold voltage to the second threshold voltage is substantially in a range from 1.1 to 1.5.

9. The semiconductor device of claim 7, wherein a ratio of a width of the edge region to a width of the channel region in the channel width direction is substantially in a range from about 0.02 to about 0.1.

10. The semiconductor device of claim 1, further comprising a pair of lightly-doped regions on the two opposing sides of the channel region in the channel length direction, and between the channel region and the pair of source/drain regions respectively, wherein a doping type of the pair of the lightly-doped regions and the pair of source/drain regions is complementary to the doping type of the channel region and the threshold voltage adjusting region.

11. A semiconductor device, comprising:

a semiconductor substrate;

an isolation structure in the semiconductor substrate;

a gate electrode over the semiconductor substrate;

a channel region between the semiconductor substrate and the gate electrode, wherein the channel region includes a central region, and an edge region adjoining to the central region in a channel width direction;

a pair of source/drain regions adjacent to two opposing sides of the channel region in a channel length direction; and

a threshold voltage adjusting region adjacent to two opposing sides of the channel region in the channel width direction, and in a sidewall and a bottom of the isolation structure,

wherein a first threshold voltage of the semiconductor device at the edge region is higher than a second threshold voltage of the semiconductor device in the central region.

12. The semiconductor device of claim 11, wherein a ratio of the first threshold voltage to the second threshold voltage is substantially in a range from 1.2 to 1.4.

13. The semiconductor device of claim 11, further comprising a threshold voltage adjusting region adjacent to the edge region of the channel region in the channel width direction.

14. The semiconductor device of claim 13, wherein a ratio of a width of the edge region to a width of the channel region in the channel width direction is substantially in a range from about 0.02 to about 0.1.

15. The semiconductor device of claim 13, wherein the isolation structure comprises a shallow trench isolation (STI) in a trench of the semiconductor substrate.

16. A method for manufacturing a semiconductor device, comprising:

receiving a semiconductor substrate;

forming a channel region in the semiconductor substrate;

forming a threshold voltage adjusting region in a sidewall and a bottom of an isolation structure to locally adjust a threshold voltage of the channel region to render a first threshold voltage of an edge region of the channel region higher than a second threshold voltage of a central region of the channel region;

forming a gate electrode over the semiconductor substrate; and

forming a pair of source/drain regions in the semiconductor substrate.

17. The method of claim 16, wherein the threshold voltage adjusting region and the channel region have the same doping type, and a doping concentration of the threshold voltage adjusting region is higher than a doping concentration of the channel region.

18. The method of claim 16, further comprising:

recessing the semiconductor substrate to form a trench;

performing an ion implantation to form a threshold voltage adjusting region in a sidewall and a bottom of the trench; and

forming a trench isolation in the trench.

19. The method of claim 18, wherein the ion implantation is performed at a tilt angle.