Semiconductor device and manufacturing method thereof

• US 10,340,366 B2
• Filed: 07/18/2017
• Issued: 07/02/2019
• Est. Priority Date: 05/15/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Cheng-Yi, Yeh, Chih Chieh, Chang, Chih-Sheng, Chiang, Hung-Li, Chen, Hung-Ming, Yeo, Yee-Chia
• Primary Examiner(s): Sengdara, Vongsavanh
• Application Number:
  US15/653,094
• Publication Number:
  US 20170317193A1
• Time in Patent Office: 714 Days
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Claims

1. A method of manufacturing a semiconductor device including a Fin FET, the method comprising:

forming a fin structure over a substrate, the fin structure extending in a first direction and including an upper layer, a part of the upper layer being exposed from an isolation insulating layer;

forming a dummy gate structure over a part of the fin structure, the dummy gate structure extending in a second direction crossing the first direction;

removing the dummy gate structure and forming a gate structure in a region in which the dummy gate structure is removed;

forming an interlayer dielectric layer over the fin structure and the gate structure;

forming a contact hole in the interlayer dielectric layer so that a part of the fin structure is exposed;

forming a source/drain structure on the exposed fin structure;

directly depositing a cap layer, by using a first gas and a second gas, on the source/drain structure, the cap layer covering a bottom surface and sidewalls of the contact hole;

forming a dielectric layer over the cap layer; and

forming a contact metal layer over the dielectric layer.

2. The method of claim 1, further comprising forming an alloy layer between the cap layer and the contact metal layer.

3. The method of claim 2, further comprising planarizing the contact metal layer, the alloy layer, and the cap layer disposed over the interlayer dielectric layer.

4. The method of claim 1, wherein:

the fin structure is made of germanium or germanium compound, and

the cap layer includes a silicon compound.

5. The method of claim 4, wherein:

the silicon compound is silicon phosphide, and

the first gas is a silicon containing gas and the second gas is a phosphorous containing gas.

6. The method of claim 1, wherein:

the fin structure is made of germanium or germanium compound, and

the dielectric layer includes at least one selected from the group consisting of silicon nitride, aluminum oxide and lanthanum oxide.

7. The method of claim 6, wherein:

the cap layer includes silicon phosphide, and

the first gas is a silicon containing gas and the second gas is a phosphorous containing gas.

8. The method of claim 1, wherein the source/drain structure includes germanium phosphide.

9. A method of manufacturing a semiconductor device including a Fin FET, the method comprising:

forming a fin structure over a substrate, the fin structure extending in a first direction and including an upper layer, a part of the upper layer being exposed from an isolation insulating layer;

forming a gate structure over a part of the fin structure, the gate structure extending in a second direction crossing the first direction;

forming an interlayer dielectric layer over the fin structure and the gate structure;

forming a contact hole in the interlayer dielectric layer so that a part of the fin structure is exposed;

forming a source/drain structure on the exposed fin structure;

directly depositing a cap layer, by using a first gas and a second gas, on the source/drain structure, the cap layer covering a bottom surface and sidewalls of the contact hole; and

forming a contact metal layer over the cap layer.

10. The method of claim 9, further comprising forming an alloy layer between the cap layer and the contact metal layer.

11. The method of claim 9, wherein:

fin structure is made of germanium or germanium compound, and

the cap layer includes a silicon compound.

12. The method of claim 11, wherein:

the silicon compound is silicon phosphide, and

the first gas is a silicon containing gas and the second gas is a phosphorous containing gas.

13. The method of claim 9, wherein:

the fin structure is made of germanium or germanium compound, and

the dielectric layer includes at least one selected from the group consisting of silicon nitride, aluminum oxide and lanthanum oxide.

14. The method of claim 13, wherein:

the cap layer includes silicon phosphide, and

the first gas is a silicon containing gas and the second gas is a phosphorous containing gas.

15. The method of claim 9, wherein the source/drain structure includes germanium phosphide.

16. A method of manufacturing a semiconductor device including a Fin FET, the method comprising:

forming a fin structure over a substrate, the fin structure extending in a first direction and including an upper layer, a part of the upper layer being exposed from an isolation insulating layer;

forming a gate structure over a part of the fin structure, the gate structure extending in a second direction crossing the first direction;

forming an interlayer dielectric layer over the fin structure and the gate structure;

forming a contact hole in the interlayer dielectric layer so that a part of the fin structure is exposed;

forming a source/drain structure on the exposed fin structure;

directly depositing forming a cap layer, by using a first gas and a second gas, on the source/drain structure, the cap layer covering a bottom surface and sidewalls of the contact hole;

forming a contact metal layer over the cap layer; and

performing a planarization process to remove portions of the contact metal layer and the cap layer over the interlayer dielectric layer.

17. The method of claim 16, wherein:

the fin structure is made of germanium or germanium compound.

18. The method of claim 16, wherein the source/drain structure includes germanium phosphide.

19. The method of claim 16, wherein the interlayer dielectric layer has a multilayer structure including a first insulating layer and a second insulating layer.

20. The method of claim 19, wherein the first insulating layer is made of silicon nitride, and the second insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluoride-doped silicate glass (FSG), or a low-K dielectric material.

21. The method of claim 16, wherein:

the cap layer includes a silicon compound including silicon phosphide, and

the first gas is a silicon containing gas and the second gas is a phosphorous containing gas.