Semiconductor device having stressor layer

• US 10,340,383 B2
• Filed: 09/27/2016
• Issued: 07/02/2019
• Est. Priority Date: 03/25/2016
• Status: Active Grant

• Current Assignee: National Taiwan University (Government of The Republic of China), Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lan, Huang-Siang, Liu, CheeWee, Liu, Chi-Wen, Huang, Shih-Hsien, Wong, I-Hsieh, Yeh, Hung-Yu, Tsai, Chung-En
• Primary Examiner(s): Landau, Matthew C
• Assistant Examiner(s): Hatzilambrou, Mark
• Application Number:
  US15/277,079
• Publication Number:
  US 20170278968A1
• Time in Patent Office: 1,008 Days
• CPC Class Codes: H01L 21/02535 including tin
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 10¹⁹ atoms cm⁻³ or less of a dopant, and a portion of the fin under the gate structure is a channel region.

Claims

1. A semiconductor device comprising:

a fin extending along a first direction over a semiconductor substrate;

a gate structure extending in a second direction overlying the fin,

wherein the gate structure comprises;

a gate dielectric layer overlying the fin;

a gate electrode overlying the gate dielectric layer; and

insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction;

a source/drain region in the fin in a region adjacent the gate structure,

wherein the source/drain region consists essentially of Ge or SiGe and a first dopant; and

a stressor layer between the source/drain region and the semiconductor substrate,

wherein the stressor layer includes GeSn or SiGeSn containing 10¹⁹ atoms cm<sup>−

3</sup> or less of a second dopant, and

a portion of the fin under the gate structure is a channel region.

2. The semiconductor device of claim 1, wherein the stressor layer comprises GeSn or SiGeSn containing less than 10¹⁸ atoms cm⁻

3 of the second dopant.

3. The semiconductor device of claim 1, wherein the stressor layer comprises undoped GeSn or undoped SiGeSn.

4. The semiconductor device of claim 1, wherein the channel region comprises Ge, SiGe, GeSn, or SiGeSn.

5. The semiconductor device of claim 1, wherein the stressor layer extends along sidewalls of the channel region forming an L-shaped stressor layer.

6. The semiconductor device of claim 1, further comprising a strain relaxed buffer layer between the stressor layer and the semiconductor substrate.

7. The semiconductor device of claim 6, wherein the stressor layer is embedded in the strain relaxed buffer layer.

8. The semiconductor device of claim 6, wherein the channel region overlies the strain relaxed buffer layer and the stressor layer extends along sidewalls of the channel region.

9. The semiconductor device of claim 6, wherein the strain relaxed buffer layer comprises Ge, SiGe, SiGeSn, or GeSn.

10. The semiconductor device of claim 1, wherein a concentration of the first dopant in the source/drain region is greater than 10²⁰ atoms cm⁻

3.

11. A semiconductor device comprising:

a fin extending along a first direction over a semiconductor substrate;

a gate structure extending in a second direction overlying the fin,

wherein the gate structure comprises;

a gate dielectric layer overlying the fin; and

a gate electrode overlying the gate dielectric layer;

source/drain regions consisting essentially of Ge or SiGe and a first dopant in the fin on opposing sides of the gate structure,

wherein the gate dielectric layer is located above the source/drain regions;

stressor layers including GeSn or SiGeSn and a second dopant between the source/drain regions and the semiconductor substrate; and

a channel region immediately adjacent the stressor layers and under the gate structure.

12. The semiconductor device of claim 11, wherein an upper surface of the gate dielectric layer is located a further distance from the semiconductor substrate than an upper surface of the source/drain regions.

13. The semiconductor device of claim 11, wherein the first dopant is Ga or B and the second dopant is Ga, B, Al, or In.

14. The semiconductor device of claim 11, further comprising a strain relaxed buffer layer between the stressor layer and the semiconductor substrate.

15. The semiconductor device of claim 14, wherein the strain relaxed buffer layer includes Si_1-x-yGe_xSn_y, wherein x ranges from 0.3 in a portion of the strain relaxed buffer layer adjacent the semiconductor substrate to 0.7 in a portion of the strain relaxed buffer layer adjacent the stressor layer, and x+y≤

1.

16. A semiconductor device comprising:

a fin extending along a first direction over a semiconductor substrate;

a gate structure extending in a second direction overlying the fin,

wherein the gate structure comprises;

a gate dielectric layer overlying the fin;

a gate electrode overlying the gate dielectric layer; and

insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction,

wherein a portion of the fin under the gate structure is a channel region;

a source/drain region in the fin in a region adjacent the gate structure,

wherein the source/drain region includes a source/drain layer, and

the source/drain layer consists essentially of Ge or SiGe and a first dopant; and

an L-shaped stressor layer made of GeSn or SiGeSn,

wherein the L-shaped stressor layer has a bottom portion and an upper portion,

wherein the bottom portion of the L-shaped stressor layer is between the source/drain layer and the semiconductor substrate, and

the upper portion of the L-shaped stressor layer extends vertically between the source/drain layer and the channel region from the bottom portion of the L-shaped stressor layer to an upper surface of the source/drain layer.

17. The semiconductor device of claim 16, wherein the upper portion of the L-shaped stressor layer is vertically aligned with an outer side surface of the insulating gate sidewalls.

18. The semiconductor device of claim 16, wherein the first dopant is Ga or B.

19. The semiconductor device of claim 16, further comprising a strain relaxed buffer layer between the stressor layer and the semiconductor substrate.

20. The semiconductor device of claim 19, wherein the strain relaxed buffer layer includes Si_1-x-yGe_xSn_y, wherein x ranges from 0.3 in a portion of the strain relaxed buffer layer adjacent the semiconductor substrate to 0.7 in a portion of the strain relaxed buffer layer adjacent the stressor layer, and x+y≤

1.