Switching circuit

• US 10,340,879 B2
• Filed: 10/18/2017
• Issued: 07/02/2019
• Est. Priority Date: 02/18/2015
• Status: Active Grant

• Current Assignee: ASM America Incorporated (ASM International NV)
• Original Assignee: Reno Technologies Inc.
• Inventors: Mavretic, Anton, Costanzo, Ian M., Decker, Ronald Anthony
• Primary Examiner(s): Jones, Stephen E.
• Assistant Examiner(s): Outten, Samuel S
• Application Number:
  US15/787,374
• Publication Number:
  US 20180041183A1
• Time in Patent Office: 622 Days
• Field of Search: 333 32
• CPC Class Codes: G01R 19/165 Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
• CPC Class Codes: H01J 2237/334 Etching
• CPC Class Codes: H01J 37/32082 Radio frequency generated discharge H01J37/32357, H01J37/32366, H01J37/32394 and H01J37/32403 take precedence
• CPC Class Codes: H01J 37/32183 Matching circuits
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/01 Resonant DC/DC converters
• CPC Class Codes: H02M 3/33569 having several active switching elements H02M3/3353 takes precedence
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H03H 7/40 Automatic matching of load impedance to source impedance
• CPC Class Codes: H03K 17/102 : in field-effect transistor switches
• CPC Class Codes: H03K 17/687 : the devices being field-effect transistors
• CPC Class Codes: H03K 17/691 : using transformer coupling
• CPC Class Codes: H03K 17/7955 : using phototransistors
• CPC Class Codes: H03K 2017/6875 : using self-conductive, depletion FETs
• CPC Class Codes: H04B 1/44 : Transmit/receive switching

Abstract

In one embodiment, an impedance matching network is disclosed that includes a first circuit comprising a first variable component providing a first variable capacitance or inductance, and a second circuit comprising a second variable component providing a second variable capacitance or inductance. Each of the first circuit and the second circuit includes plurality of switching circuits configured to provide the first variable capacitance or inductance and the second variable capacitance or inductance. Each of the plurality of switching circuits includes a diode and a driver circuit configured to switch the diode. The driver circuit includes a first switch, a second switch coupled in series with the first switch, and a filter circuit that is coupled at a first end between the first switch and the second switch, and is operably coupled at a second end to the diode.

Claims

1. An impedance matching network comprising:

an RF input configured to couple to an RF source;

an RF output configured to couple to a load;

a first circuit comprising a first variable component providing a first variable capacitance or inductance; and

a second circuit comprising a second variable component providing a second variable capacitance or inductance;

wherein each of the first circuit and the second circuit comprises a plurality of switching circuits configured to provide the first variable capacitance or inductance and the second variable capacitance or inductance, respectively, each of the plurality of switching circuits comprising;

a diode having an anode that is operably coupled to a ground; and

a driver circuit operably coupled to a cathode of the diode and configured to switch the diode, the driver circuit comprising;

a first switch;

a second switch coupled in series with the first switch;

a filter circuit that is coupled at a first end between the first switch and the second switch, and is operably coupled at a second end to the diode;

a first driver operably coupled to the first switch;

a second driver operably coupled to the second switch; and

a third driver operably coupled to the first and second drivers, the third driver configured to;

provide a first signal to the first driver; and

provide a second driving signal to the second driver;

wherein, in providing the first and second signals, the third driver is configured to increase and decrease a duration of a dead time between (a) the third driver driving the first driver on and the second driver off, or (b) the third driver driving the second driver on and the first driver off.

2. A switching circuit comprising:

a diode; and

a driver circuit configured to switch the diode, the driver circuit comprising;

a first switch;

a second switch coupled in series with the first switch; and

a filter circuit that is coupled at a first end between the first switch and the second switch, and is operably coupled at a second end to the diode;

a first driver operably coupled to the first switch;

a second driver operably coupled to the second switch; and

a third driver operably coupled to the first and second drivers, the third driver configured to;

provide a first signal to the first driver; and

provide a second driving signal to the second driver;

wherein, in providing the first and second signals, the third driver is configured to increase and decrease a duration of a dead time between (a) the third driver driving the first driver on and the second driver off, or (b) the third driver driving the second driver on and the first driver off.

3. A semiconductor processing tool comprising:

a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate; and

an impedance matching circuit operably coupled to the plasma chamber, matching circuit comprising;

an RF input configured to be operably coupled to an RF source;

an RF output operably coupled to the plasma chamber;

a first circuit comprising a first variable component providing a first variable capacitance or inductance; and

a second circuit comprising a second variable component providing a second variable capacitance or inductance;

wherein each of the first circuit and the second circuit comprises a plurality of switching circuits configured to provide the first variable capacitance or inductance and the second variable capacitance or inductance, respectively, each of the plurality of switching circuits comprising;

a diode; and

a driver circuit operably coupled to the diode and configured to switch the diode, the driver circuit comprising;

a first switch;

a second switch coupled in series with the first switch; and

a filter circuit that is coupled at a first end between the first switch and the second switch, and is operably coupled at a second end to the diode;

a first driver operably coupled to the first switch;

a second driver operably coupled to the second switch; and

a third driver operably coupled to the first and second drivers, the third driver configured to;

provide a first signal to the first driver; and

provide a second driving signal to the second driver;

wherein, in providing the first and second signals, the third driver is configured to increase and decrease a duration of a dead time between (a) the third driver driving the first driver on and the second driver off, or (b) the third driver driving the second driver on and the first driver off.

4. A method of matching an impedance, the method comprising:

operably coupling a matching network between an RF source and a load, the matching network comprising;

a first circuit comprising a first variable component providing a first variable capacitance or inductance; and

a second circuit comprising a second variable component providing a second variable capacitance or inductance;

wherein each of the first circuit and the second circuit comprises a plurality of switching circuits, each of the plurality of switching circuits comprising;

a diode; and

a driver circuit configured to switch the diode, the driver circuit comprising;

a first switch;

a second switch coupled in series with the first switch;

a filter circuit that is coupled at a first end between the first switch and the second switch, and is operably coupled at a second end to the diode;

a first driver operably coupled to the first switch;

a second driver operably coupled to the second switch; and

a third driver operably coupled to the first and second drivers;

providing, by the third driver, a first signal to the first driver and a second signal to the second driver, wherein, in providing the first and second signals, the third driver is configured to increase and decrease a duration of a dead time between (a) the third driver driving the first driver on and the second driver off, or (b) the third driver driving the second driver on and the first driver off; and

providing the first variable capacitance or inductance or the second variable capacitance or inductance, respectively, by, for at least one switching circuit of the plurality of switching circuits, either switching on the first switch and switching off the second switch, or switching off the first switch and switching on the second switch.

5. The method of claim 4 wherein the diode is a PIN diode.

6. The method of claim 4 wherein the first and second switches are metal-oxide semiconductor field-effect transistors (MOSFETs).

7. The method of claim 4 wherein the filter circuit comprises an LC circuit.

8. The method of claim 4 wherein a drain of the first switch is coupled to a source of the second switch.

9. The method of claim 4 wherein the second end of the filter circuit is coupled to a cathode of the diode.

10. The method of claim 4

wherein the first and second signals substantially asynchronously drive the first and second drivers on and off.

11. The method of claim 4 wherein the duration of the dead time can be adjusted by varying a resistance of a potentiometer coupled to the third driver.

12. The method of claim 4 wherein the duration of the dead time is based on the inductance of an inductor forming part of the filter circuit.

13. A method of switching a diode comprising:

coupling a first switch and a second switch in series;

coupling a filter circuit at a first end between the first switch and the second switch;

operably coupling the filter circuit at a second end to a diode to be switched;

operably coupling a first driver to the first switch;

operably coupling a second driver to the second switch; and

operably coupling a third driver to the first and second drivers;

providing, by the third driver, a first signal to the first driver and a second signal to the second driver, wherein, in providing the first and second signals, the third driver is configured to increase and decrease a duration of a dead time between (a) the third driver driving the first driver on and the second driver off, or (b) the third driver driving the second driver on and the first driver off; and

either switching on the first switch and switching off the second switch, or switching off the first switch and switching on the second switch.

14. The method of claim 13 wherein the diode is a PIN diode.

15. The method of claim 13 wherein the first and second switches are metal-oxide semiconductor field-effect transistors (MOSFETs).

16. The method of claim 13 wherein the filter circuit comprises an LC circuit.

17. The method of claim 13 wherein a drain of the first switch is coupled to a source of the second switch.

18. The method of claim 13 wherein the second end of the filter circuit is coupled to a cathode of the diode.

19. The method of claim 13

wherein the first and second signals substantially asynchronously drive the first and second drivers on and off.

20. The method of claim 13 wherein the duration of the dead time can be adjusted by varying a resistance of a potentiometer coupled to the third driver.

21. A method of fabricating a semiconductor, the method comprising:

placing a substrate in a plasma chamber configured to deposit a material layer onto the substrate or etch a material layer from the substrate;

energizing plasma within the plasma chamber by coupling RF power from an RF source into the plasma chamber to perform a deposition or etching; and

while energizing the plasma, carrying out an impedance match by an impedance matching network coupled between a load and an RF source, wherein the impedance matching network comprises;

an RF input configured to couple to an RF source;

an RF output configured to couple to a load;

a first circuit comprising a first variable component providing a first variable capacitance or inductance; and

a second circuit comprising a second variable component providing a second variable capacitance or inductance;

wherein each of the first circuit and the second circuit comprises a plurality of switching circuits configured to provide the first variable capacitance or inductance and the second variable capacitance or inductance, respectively, each of the plurality of switching circuits comprising;

a diode; and

a driver circuit configured to switch the diode, the driver circuit comprising;

a first switch;

a second switch coupled in series with the first switch;

a filter circuit that is coupled at a first end between the first switch and the second switch, and is operably coupled at a second end to the diode;

a first driver operably coupled to the first switch;

a second driver operably coupled to the second switch; and

a third driver operably coupled to the first and second drivers, the third driver configured to;

 

provide a first signal to the first driver; and

 

provide a second driving signal to the second driver;

 

wherein, in providing the first and second signals, the third driver is configured to increase and decrease a duration of a dead time between (a) the third driver driving the first driver on and the second driver off, or (b) the third driver driving the second driver on and the first driver off.