Analog to digital convertor (ADC) using a common input stage and multiple parallel comparators

• US 10,340,938 B1
• Filed: 04/24/2018
• Issued: 07/02/2019
• Est. Priority Date: 04/24/2018
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Eitan, Roee, Livne, Ram, Khairi, Ahmad, Krupnik, Yoel, Cohen, Ariel
• Primary Examiner(s): Young, Brian K
• Application Number:
  US15/961,460
• Time in Patent Office: 434 Days
• Field of Search: 341155, 341110
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/356191 with synchronous operation
• CPC Class Codes: H03K 5/22 Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral indicating phase difference of two cyclic pulse trains G01R25/00
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H03M 1/38 sequentially only, e.g. successive approximation type converting more than one bit per step H03M1/14
• CPC Class Codes: H03M 1/40 recirculation type
• CPC Class Codes: H03M 1/462 Details of the control circuitry, e.g. of the successive approximation register

Abstract

An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.

Claims

1. An Analog to Digital converter (ADC) comprising:

a first circuitry to sample an analog input signal;

a summation block to iteratively generate a subtraction signal, which is based on a difference between the analog input signal and a feedback signal;

a second circuitry to receive the subtraction signal; and

a plurality of comparison and latch circuitries arranged in parallel, wherein individual ones of the plurality of parallel comparison and latch circuitries is to sequentially receive an output of the second circuitry.

2. The ADC of claim 1, wherein the plurality of comparison and latch circuitries is to generate a digital output that is a digital representation of the analog input signal.

3. The ADC of claim 2, wherein a number of comparison and latch circuitries in the plurality of comparison and latch circuitries is equal to a number of bits in the digital output.

4. The ADC of claim 2, wherein at least one comparison and latch circuitry is to store a corresponding bit of a plurality of bits of the digital output.

5. The ADC of claim 2, wherein the plurality of comparison and latch circuitries include a first comparison and latch circuitry and a second comparison and latch circuitry, and wherein:

the first comparison and latch circuitry is to perform a comparison operation to determine a value of a first bit of the digital output;

the second comparison and latch circuitry is to perform a comparison operation to determine a value of a second bit of the digital output; and

the ADC comprises a comparison completion indication circuitry to trigger initiation of the comparison operation of the second comparison and latch circuitry, in response to a completion of the comparison operation and a latching operation in the first comparison and latch circuitry.

6. The ADC of claim 5, wherein the first bit and the second bit are two immediate adjacent bits in the digital output, and wherein the first bit has higher weight than the second bit in the digital output.

7. The ADC of claim 2, wherein the plurality of comparison and latch circuitries include:

a first comparison and latch circuitry; and

a second comparison and latch circuitry,

and wherein;

the first comparison and latch circuitry is to perform a comparison operation to update a first value of a Digital to Analog Converter (DAC);

the second comparison and latch circuitry is to perform a comparison operation to update a second value of the DAC, and

the DAC is to generate the feedback signal.

8. The ADC of claim 2, wherein the plurality of comparison and latch circuitries include:

a first comparison and latch circuitry; and

a second comparison and latch circuitry,

and wherein;

the first comparison and latch circuitry is to perform a comparison operation to update a first value of a Digital to Analog Converter (DAC);

the second comparison and latch circuitry is to perform a comparison operation to update a second value of the DAC, and

the ADC comprises a logic to synchronously trigger initiation of the comparison operation of the second comparison and latch circuitry.

9. The ADC of claim 2, wherein an individual one of the comparison and latch circuitries comprises:

one or more switches to selectively couple the common input stage to the first comparison and latch circuitry;

one or more switchable loads;

a latch to regenerate and maintain a result of a comparison operation in the first comparison and latch circuitry; and

a latch reset mechanism to reset the latch prior to the comparison operation.

10. The ADC of claim 9, wherein the latch comprises:

a first pair of cross-coupled transistors comprising a first transistor and a second transistor; and

a second pair of cross-coupled transistors comprising a third transistor and a fourth transistor, wherein the first transistor is coupled in series with the third transistor, wherein the second transistor is coupled in series with the fourth transistor, wherein a first output node is coupled between the first and third transistors, and wherein a second output node is coupled between the second and fourth transistors.

11. The ADC of claim 10, wherein the latch reset mechanism comprises one or more of:

a first switch to selectively couple the first output node to a ground terminal;

a second switch to selectively couple the second output node to the ground terminal;

or

a third switch to selectively couple the first and second output nodes.

12. The ADC of claim 9, wherein the latch comprises:

a first inverter and a second inverter arranged in a clocked back-to-back invertor arrangement.

23. The ADC of claim 1, wherein:

the plurality of comparison and latch circuitries include;

a first comparison and latch circuitry, and a second comparison and latch circuitry; and

individual ones of the plurality of parallel comparison and latch circuitries is to sequentially receive the output of the second circuitry such that;

the second comparison and latch circuitry is to receive the output of the second circuitry subsequent to the output of the second circuitry being received by the first comparison and latch circuitry.

13. A system comprising:

a memory to store instructions;

a processor coupled to the memory, the processor to execute the instructions;

a wireless interface to allow the processor to communicate with another system; and

an Analog to Digital converter (ADC) coupled to at least one of the memory, the processor, the wireless interface, or another component of the system, the ADC comprising;

a plurality of comparison and latch circuitries arranged in parallel, wherein the plurality of comparison and latch circuitries is to generate a digital output that is a digital representation of an analog input signal, wherein an individual comparison and latch circuitry is to determine a corresponding bit of a plurality of bits of the digital output, and wherein the plurality of comparison and latch circuitries comprises at least a first comparison and latch circuitry and a second comparison and latch circuitry, and

a comparison completion indication circuitry to trigger activation of the second comparison and latch circuitry, in response to a completion of a comparison operation and a latching operation in the first comparison and latch circuitry.

14. The system of claim 13, wherein the comparison completion indication circuitry is to generate one or more control signals for activation and operation of the second comparison and latch circuitry, in response to differential outputs of the first comparison and latch circuitry being latched in the first comparison and latch circuitry.

15. The system of claim 14, wherein the comparison completion indication circuitry comprises a NOR logical gate to:

receive the two outputs of the first comparison and latch circuitry; and

generate a ready signal, where the ready signal is to trigger activation of the second comparison and latch circuitry after a configurable delay.

16. The system of claim 15, wherein the ready signal is to initially activate a reset of the second comparison and latch circuitry, and subsequently trigger activation of a comparison operation in the second comparison and latch circuitry.

17. The system of claim 13, wherein:

the first comparison and latch circuitry is to perform the comparison operation to determine a value of a first bit of the digital output;

the second comparison and latch circuitry is to perform the comparison operation to determine a value of a second bit of the digital output;

the first bit and the second bit are two immediate adjacent bits in a digital output of the ADC; and

the first bit has higher weight than the second bit in the digital output.

18. An apparatus comprising:

a first circuitry to receive a first input signal and a second input signal; and

a plurality of second circuitries arranged in parallel, wherein individual ones of the plurality of second circuitries is to sequentially receive an output of the first circuitry, and wherein a circuitry of the plurality of second circuitries comprise;

one or more switches to selectively couple the first circuitry;

one or more switchable loads, wherein the first circuitry and the one or more switchable loads is to compare the first and second input signals, and output the comparison results in a first output node and a second output node;

a latch to regenerate and maintain the comparison result in the first and second output nodes; and

a latch reset mechanism to reset the latch prior to the comparison.

19. The apparatus of claim 18, wherein the first circuitry comprises:

a first transistor coupled between a supply and a first switch of the one or more switches, the first transistor being controlled by the first input signal; and

a second transistor coupled between the supply and a second switch of the one or more switches, the second transistor being controlled by the second input signal.

20. The apparatus of claim 19, wherein the one or more switchable loads comprises:

a first diode connected transistor coupled between the first switch and a ground terminal; and

a second diode connected transistor coupled between the second switch and the ground terminal.

21. The apparatus of claim 20, wherein the circuitry of the plurality of second circuitries further comprise:

the first output node coupled between the first switch and the first diode connected transistor;

the second output node coupled between the second switch and the second diode connected transistor; and

a latch coupled to the first and second output nodes, wherein the latch is to regenerate differential output signal in the first and second output nodes, and to maintain the signals in the first and second output nodes.

22. The apparatus of claim 18, wherein the first and second input signals are a differential input signal, and the first output node and the second output node is to output a differential output signal.

24. An apparatus comprising:

a plurality of comparison and latch circuitries, wherein an output of an individual one of the plurality of comparison and latch circuitries is to sequentially trigger initiation of a comparison and latch operation by a subsequent comparison and latch circuitry of the plurality of comparison and latch circuitries; and

a trans-conductance input circuitry coupled to the plurality of comparison and latch circuitries, wherein the trans-conductance input circuitry is to receive a differential input and generate current for one of the individual one of the plurality of comparison and latch circuitries.

25. The apparatus of claim 24, wherein the trans-conductance input circuitry is a single differential stage shared by the plurality of comparison and latch circuitries.