Low power high speed receiver with reduced decision feedback equalizer samplers

• US 10,341,145 B2
• Filed: 03/03/2015
• Issued: 07/02/2019
• Est. Priority Date: 03/03/2015
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Musah, Tawfiq, Venkatram, Hariprasath, Casper, Bryan K.
• Primary Examiner(s): Tadese, Berhanu
• Application Number:
  US14/637,291
• Publication Number:
  US 20160261435A1
• Time in Patent Office: 1,582 Days
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 7/0062 detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions

Abstract

Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

Claims

1. An apparatus comprising:

an analog to digital converter (ADC) to operate as a Variable Gain Amplifier (VGA) and as a set of samplers to sample data output from the ADC according to a clock signal, wherein the ADC is to operate as a VGA when threshold levels to the ADC are adjusted,

wherein the set of samples have programmable threshold, and wherein the set of samplers comprise clocked comparators; and

a Clock Data Recovery (CDR) circuit coupled to the ADC, wherein the CDR comprises a phase detector which is to instruct an oscillator to adjust a phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data, wherein the clock signal with adjusted phase is provided to the ADC.

2. The apparatus of claim 1, wherein the set of samplers perform a dual operation of sampling the data output and for generating an error signal for the CDR.

3. The apparatus of claim 1 comprises a Continuous Time Linear Equalizer (CTLE) coupled to an input of the ADC.

4. The apparatus of claim 1, wherein the set of samplers is to provide quantized data for the phase detector of the CDR.

5. The apparatus of claim 4 comprises a thermometer-to-binary converter to convert the quantized data from a thermometer code to a binary code.

6. The apparatus of claim 5 comprises:

a multiplexer for receiving the sampled data adjusted by a first weight and for receiving the sampled data adjusted by a second weight; and

a delay unit to receive output of multiplexer and generate a delayed output for the CDR.

7. The apparatus of claim 6, wherein the first and second weights have substantially equal magnitudes but different signs.

8. The apparatus of claim 6, wherein the phase detector is to receive the binary code and the delayed output from the delay unit, and is to generate an output indicating adjustment to the phase for the clock signal.

9. The apparatus of claim 8, wherein the phase detector is a multi-bit phase detector, and wherein the output of the phase detector indicates direction and amount of phase adjustment for the clock signal.

10. The apparatus of claim 8, wherein the CDR comprises a loop filter coupled to the output of the phase detector.

11. The apparatus of claim 10, wherein the CDR comprises a digital controlled oscillator (DCO) to receive output of the loop filter and to provide the clock signal to the set of samplers.

12. The apparatus of claim 1, wherein a Transmit Linear Equalizer (TXLE) provides data for the ADC.

17. The system of claim 1, wherein the processor comprises:

a multiplexer for receiving the sampled data adjusted by a first weight and for receiving the sampled data adjusted by a second weight; and

a delay unit to receive output of multiplexer and generate a delayed output for the CDR.

18. The system of claim 17, wherein the first and second weights have substantially equal magnitudes but different signs.

19. The system of claim 17, wherein the phase detector is to receive the binary code and the delayed output from the delay unit, and is to generate an output indicating adjustment to the phase for the clock signal.

13. A system comprising:

a memory;

a processor coupled to the memory, the processor having a receiver which comprises;

an analog to digital converter (ADC) to operate as a Variable Gain Amplifier (VGA) and as a set of samplers to sample data output from the ADC according to a clock signal, wherein the ADC is to operate as a VGA when threshold levels to the ADC are adjusted

wherein the set of samples have programmable threshold, and wherein the set of samplers comprise clocked comparators; and

a Clock Data Recovery (CDR) circuit coupled to the ADC, wherein the CDR comprises a phase detector which is to instruct an oscillator to adjust a phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data, wherein the clock signal with adjusted phase is provided to the ADC; and

a wireless interface to allow the processor to communicate with another device.

14. The system of claim 13, wherein the processor comprises a Continuous Time Linear Equalizer (CTLE) coupled to an input of the ADC.

15. The system of claim 14, wherein the set of samplers to provide quantized data for a phase detector of the CDR.

16. The system of claim 15, wherein the processor comprises a thermometer-to-binary converter to convert the quantized data from a thermometer code to a binary code.

20. An apparatus comprising:

an analog-to-digital converter (ADC) to sample data output according to a clock signal, wherein the set of samples have programmable threshold; and

a Clock Data Recovery (CDR) circuit coupled to the ADC, wherein the CDR is to adjust a phase of a clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data, wherein the clock signal with adjusted phase is provided to the ADC.

21. The apparatus of claim 20, wherein the ADC is to operate as a Variable Gain Amplifier (VGA) when threshold levels to the ADC are adjusted.

22. The apparatus of claim 21, wherein the ADC is to operate as a set of samplers to sample data output from the ADC according to the clock signal wherein the set of samples have programmable threshold, and wherein the set of samplers comprise clocked comparators.

23. The apparatus of claim 22, wherein the set of samplers are re-used for channel output quantization to enable multi-bit adaption and timing recovery.

24. The apparatus of claim 20, wherein reference levels to the ADC are adjustable to with reference to an input signal, and wherein an output of the ADC is to represent a lower or higher gain of the input signal.