Image sensors with electronic shutter

• US 10,341,571 B2
• Filed: 06/08/2017
• Issued: 07/02/2019
• Est. Priority Date: 06/08/2016
• Status: Active Grant

• Current Assignee: InVisage Technologies, Inc. (Apple Inc.)
• Original Assignee: InVisage Technologies, Inc. (Apple Inc.)
• Inventors: Mandelli, Emanuele, Boisvert, David Michael, Bock, Nikolai
• Primary Examiner(s): Alavi, Amir
• Application Number:
  US15/617,284
• Publication Number:
  US 20170359497A1
• Time in Patent Office: 754 Days
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H04N 23/73 by influencing the exposure time
• CPC Class Codes: H04N 25/53 Control of the integration time
• CPC Class Codes: H04N 25/532 by controlling global shutters in CMOS SSIS
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/622 by controlling anti-blooming drains
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/71 Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion
• CPC Class Codes: H04N 25/7795 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

In various embodiments, an image sensor and related methods of operation of the image sensor are disclosed. In an embodiment, an image sensor includes at least one pixel. The at least one pixel including a transistor to couple an overflow capacitor to a floating diffusion node. Under a low light condition, photocharge is to be collected in a floating diffusion, but substantially not into an overflow node. Under a high light condition, photocharge is to overflow into the overflow node. Other sensors and related operations are disclosed.

Claims

1. An image sensor, comprising:

at least one pixel, the at least one pixel including a transistor to couple an overflow capacitor to a floating diffusion node;

wherein, under a low light condition, photocharge is to be collected in a floating diffusion, but not into an overflow node; and

wherein, under a high light condition, photocharge is to overflow into the overflow node.

2. The image sensor of claim 1, further comprising a comparator to inspect a signal on the floating diffusion.

3. The image sensor of claim 2, wherein an output of the comparator is to charge a capacitor to a level of the floating diffusion.

4. The image sensor of claim 2, wherein an output of the comparator is to charge a capacitor to a level of the overflow node.

5. The image sensor of claim 1, wherein the image sensor is configured to perform a pixel reset operation, the pixel reset operation including:

turning the transistor on; and

raising a potential barrier under a gate of the transistor by setting a gate voltage to a low level.

6. The image sensor of claim 1, wherein a determination is made whether to reset a pixel to reduce temporal noise is based on whether a signal output from the pixel is above a predetermined threshold level.

7. The image sensor of claim 1, wherein a gate voltage on the transistor is to be set statically to a high voltage level.

8. The image sensor of claim 7, wherein the pixel is configured to have a conversion gain of about q/(C+3C), where q is the elementary charge and C is a total capacitance of a floating diffusion node capacitor coupled to the floating diffusion node, with the gate voltage set to the high voltage level.

9. The image sensor of claim 1, wherein a gate voltage on the transistor is to be set statically to a low voltage level.

10. The image sensor of claim 9, wherein the pixel is configured to have a conversion gain of about q/C, where q is the elementary charge and C is a total capacitance of a floating diffusion node capacitor coupled to the floating diffusion node, with the gate voltage set to the low voltage level.

11. The image sensor of claim 1, wherein a gate voltage on the transistor is configured to switch between a low voltage level and a high voltage level on each line.

12. The image sensor of claim 11, wherein a voltage on a PIXOUT node is to be compared with a fixed reference voltage in a comparator.

13. The image sensor of claim 12, wherein a selection of the fixed reference voltage is to be determined for one of two nodes including a low dynamic range mode with lower noise or a high dynamic range mode with higher noise.

14. The image sensor of claim 12, wherein the reference voltage is configured to change column-to-column.

15. The image sensor of claim 12, wherein the reference voltage is configured to change pixel-to-pixel.

16. The image sensor of claim 1, wherein the pixel is configured to be reset a plurality of times to reduce temporal noise.

17. The image sensor of claim 16, wherein each of the plurality of resets is followed by an analog-to-digital conversion.

18. The image sensor of claim 16, wherein a first of the plurality of resets is followed by an analog-to-digital conversion (ADC) and subsequent ones of the plurality of resets are followed by a partial ADC operation.

19. The image sensor of claim 16, wherein an averaging operation is to be applied to signals from the plurality of resets to reduce temporal noise.

20. The image sensor of claim 16, wherein the number of the plurality of resets is four.