Combined analog architecture and functionality in a mixed-signal array
First Claim
Patent Images
1. A circuit comprising:
- a plurality of programmable digital blocks configured according to at least one configuration register, wherein at least one programmable digital block is for issuing a direct memory access (DMA) request in response to an event detected by the plurality of programmable digital blocks;
a DMA controller coupled to the at least one programmable digital block, the DMA controller for retrieving configuration information from a memory and writing the configuration information to the at least one configuration register upon receipt of the DMA request.
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Abstract
A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.
105 Citations
20 Claims
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1. A circuit comprising:
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a plurality of programmable digital blocks configured according to at least one configuration register, wherein at least one programmable digital block is for issuing a direct memory access (DMA) request in response to an event detected by the plurality of programmable digital blocks; a DMA controller coupled to the at least one programmable digital block, the DMA controller for retrieving configuration information from a memory and writing the configuration information to the at least one configuration register upon receipt of the DMA request. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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receiving a direct memory access (DMA) request from at least one of a plurality of programmable digital blocks in response to an event detected by the plurality of programmable digital blocks; retrieving configuration information using a DMA controller from a memory in response to the DMA request; and writing the program information using the DMA controller from the memory to at least one configuration register. - View Dependent Claims (9, 10, 11)
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12. A system comprising:
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a central processing unit (CPU); a memory; a programmable circuit comprising a plurality of programmable digital blocks configured according to at least one configuration register, wherein at least one programmable digital block is for issuing a direct memory access (DMA) request in response to an event detected by the plurality of programmable digital blocks; a DMA controller coupled to the at least one programmable digital block, the DMA controller for retrieving configuration information from a memory and writing the configuration information to the at least one configuration register upon receipt of the DMA request. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification