Intelligent data storage and processing using FPGA devices

• US 10,346,181 B2
• Filed: 01/29/2018
• Issued: 07/09/2019
• Est. Priority Date: 05/23/2003
• Status: Active Grant

• Current Assignee: Ip Reservoir, LLC
• Original Assignee: Ip Reservoir, LLC
• Inventors: Chamberlain, Roger D., Franklin, Mark Allen, Indeck, Ronald S., Cytron, Ron K., Cholleti, Sharath R.
• Primary Examiner(s): Fleurantin, Jean B
• Application Number:
  US15/882,679
• Publication Number:
  US 20180157504A1
• Time in Patent Office: 526 Days
• Field of Search: 707636, 707706, 707707, 707770, 707796, 707812, 711103, 711111, 711145
• CPC Class Codes: G06F 16/2455 Query execution
• CPC Class Codes: G06F 16/90335 Query processing
• CPC Class Codes: G06F 17/00 Digital computing or data processing equipment or methods, specially adapted for specific functions information retrieval, database structures or file system structures therefor G06F16/00
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06Q 40/06 Asset management; Financial planning or analysis

Abstract

Methods and systems are disclosed where a plurality of precompiled hardware templates are stored in memory, each of the hardware templates being configured for loading onto a re-configurable logic device such as a FPGA to define a data processing operation to be performed by the re-configurable logic device, each of the data processing operations defined by the precompiled hardware templates having an associated performance characteristic. A processor selects a precompiled hardware template from a plurality of the precompiled hardware templates in the memory for loading onto the re-configurable logic device based at least in part on the associated performance characteristics of the data processing operations defined by the precompiled hardware templates.

Claims

1. A data processing apparatus comprising:

a field programmable gate array (FPGA) that offloads a plurality of processing tasks from a processor within a computer system;

wherein the FPGA is configured to receive and process streaming data through a multi-functional pipeline deployed on the FPGA;

wherein the multi-functional pipeline comprises a plurality of pipelined data processing engines, each pipelined data processing engine being configured to (1) perform a processing operation on streaming data received by that data processing engine, and (2) be responsive to a control instruction that defines whether that pipelined data processing engine is an activated data processing engine or a deactivated data processing engine, wherein an activated data processing engine is configured to perform the processing operation for that data processing engine on received streaming data, and wherein a deactivated data processing engine remains in the pipeline but does not perform the processing operation for that data processing engine on received streaming data, the multi-functional pipeline thereby being configured to provide a plurality of different pipeline functions in response to control instructions that are configured to selectively activate and deactivate the pipelined data processing engines, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline at a given time.

2. The apparatus of claim 1 wherein the data processing engines include an encryption engine.

3. The apparatus of claim 2 wherein the encryption engine comprises a plurality of rounds that are fully pipelined.

4. The apparatus of claim 1 wherein at least one of the data processing engines includes logic that computes a running aggregation of data within the streaming data.

5. The apparatus of claim 1 wherein the data processing engines include a decryption engine.

6. The apparatus of claim 5 wherein the data processing engines further include a search engine downstream from the decryption engine.

7. The apparatus of claim 5 wherein the data processing engines further include an encryption engine downstream from the decryption engine, and wherein the multi-functional pipeline provides trans-encryption via the decryption engine and the downstream encryption engine.

8. The apparatus of claim 1 wherein the data processing engines include a compression engine.

9. The apparatus of claim 1 wherein the data processing engines include a decompression engine.

10. The apparatus of claim 1 wherein the data processing engines include a search engine.

11. The apparatus of claim 1 wherein a plurality of the data processing engines are arranged to provide pipelined processing of streaming DNA sequence data including matching operations on data within the streaming DNA sequence data.

12. The apparatus of claim 1 further comprising the computer system, the computer system having a bus, and wherein the computer system is configured to communicate with the FPGA over the bus to control an operation of the FPGA.

13. The apparatus of claim 12 wherein the computer system further comprises a network interface through which the streaming data is received from a network.

14. The apparatus of claim 12 wherein the computer system further comprises a storage medium from which the streaming data is read.

15. The apparatus of claim 14 wherein the storage medium comprises a disk.

16. The apparatus of claim 14 wherein a plurality of data files are stored in the storage medium, each data file being stored as a sequence of segments, each segment having a size that is a power of 2;

and

wherein the processor is configured to (1) write the data files to the storage medium as the sequence of segments, and (2) manage a flow of a plurality of the data files to the FPGA for processing via the pipeline.

17. A data processing apparatus comprising:

a processor;

a field programmable gate array (FPGA) that offloads a plurality of processing tasks from the processor;

a bus that links the processor with the FPGA; and

a network interface;

wherein the FPGA is configured to process streaming data received via the network interface;

wherein the FPGA is controllable in response to control instructions received from the processor via the bus;

wherein the FPGA comprises resident hardware logic for a plurality of data processing engines that are combinable as a processing pipeline within the FPGA;

wherein the FPGA, in response to the control instructions, controls the data processing engines to selectively tap into the streaming data to perform processing operations on the streaming data;

wherein the FPGA selectively provides a pass through path for the streaming data whereby the data processing engines do not perform processing operations on a selected portion of the streaming data; and

wherein the data processing engines comprise at least one of (1) an encryption engine, (2) a decryption engine, (3) a search engine, (4) a compression engine, (5) a decompression engine, and/or (6) an engine that computes a running aggregation of data within the streaming data.

18. The apparatus of claim 17 wherein the network interface, processor, FPGA, and bus are part of a computer server.

19. The apparatus of claim 18 further comprising a connector through which the FPGA receives the streaming data.

20. The apparatus of claim 19 wherein the connector comprises a PCI-Express connector.

21. The apparatus of claim 18 wherein the FPGA includes a control processor that manages a flow of streaming data to and from the data processing engines.

22. The apparatus of claim 18 wherein the data processing engines comprise the encryption engine.

23. The apparatus of claim 22 wherein the encryption engine comprises a plurality of rounds that are fully pipelined.

24. The apparatus of claim 18 wherein the data processing engines comprise the engine that computes the running aggregation.

25. The apparatus of claim 18 wherein the data processing engines comprise the decryption engine.

26. The apparatus of claim 25 wherein the data processing engines further comprise the search engine, wherein the search engine is downstream from the decryption engine.

27. The apparatus of claim 25 wherein the data processing engines further comprise the encryption engine, wherein the encryption engine is downstream from the decryption engine, and wherein the processing pipeline provides trans-encryption via the decryption engine and the downstream encryption engine.

28. The apparatus of claim 18 wherein the data processing engines comprise the compression engine.

29. The apparatus of claim 18 wherein the data processing engines comprise the decompression engine.

30. The apparatus of claim 18 wherein the data processing engines comprise the search engine.

31. The apparatus of claim 18 wherein a plurality of the data processing engines are arranged to provide pipelined processing of streaming DNA sequence data including matching operations on data within the streaming DNA sequence data.

32. The apparatus of claim 18 wherein the computer server further comprises a storage medium from which the streaming data is read.

33. The apparatus of claim 32 wherein the storage medium comprises a disk.

34. The apparatus of claim 18 wherein the bus also links the network interface with the FPGA.

35. A data processing apparatus comprising:

a field programmable gate array (FPGA) that offloads a plurality of processing tasks from a processor within a computer system; and

a network interface;

wherein the FPGA is configured to process streaming data received via the network interface;

wherein the FPGA comprises a multi-functional pipeline deployed thereon;

wherein the multi-functional pipeline comprises a plurality of pipelined data processing engines, each pipelined data processing engine being configured to (1) perform a processing operation on streaming data received by that data processing engine, and (2) be responsive to a control instruction that defines whether that pipelined data processing engine is an activated data processing engine or a deactivated data processing engine, wherein an activated data processing engine is configured to perform the processing operation for that data processing engine on received streaming data, and wherein a deactivated data processing engine remains in the pipeline but does not perform the processing operation for that data processing engine on received streaming data, the multi-functional pipeline thereby being configured to provide a plurality of different pipeline functions in response to control instructions that are configured to selectively activate and deactivate the pipelined data processing engines, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline at a given time.

36. The apparatus of claim 35 wherein the FPGA is part of a board that connects with the computer system via a bus.

37. The apparatus of claim 36 wherein the data processing engines include an encryption engine.

38. The apparatus of claim 37 wherein the encryption engine comprises a plurality of rounds that are fully pipelined.

39. The apparatus of claim 36 wherein at least one of the data processing engines includes logic that computes a running aggregation of data within the streaming data.

40. The apparatus of claim 36 wherein the data processing engines include a decryption engine.

41. The apparatus of claim 40 wherein the data processing engines further include a search engine downstream from the decryption engine.

42. The apparatus of claim 40 wherein the data processing engines further include an encryption engine downstream from the decryption engine, and wherein the multi-functional pipeline provides trans-encryption via the decryption engine and the downstream encryption engine.

43. The apparatus of claim 36 wherein the data processing engines include a compression engine.

44. The apparatus of claim 36 wherein the data processing engines include a decompression engine.

45. The apparatus of claim 36 wherein the data processing engines include a search engine.

46. The apparatus of claim 36 wherein a plurality of the data processing engines are arranged to provide pipelined processing of streaming DNA sequence data including matching operations on data within the streaming DNA sequence data.

47. A method comprising:

streaming data through a field programmable gate array (FPGA), wherein the FPGA includes a plurality of areas in which resident hardware logic is arranged for performing a plurality of pipelined processing operations on the streaming data, wherein the pipelined processing operations comprise at least one of (1) encryption, (2) decryption, (3) matching, (4) compression, (5) decompression, and/or (6) running aggregation;

for processing a first portion of the streaming data, (1) activating a first area of the FPGA corresponding to resident hardware logic for performing a plurality of the pipelined processing operations, (2) deactivating a second area of the FPGA corresponding to resident hardware logic for performing a second plurality of the pipelined processing operations, wherein the resident hardware logic for the deactivated second area remains resident on the FPGA while deactivated, (3) the resident hardware logic for the activated first area performing the pipelined processing operations for that resident hardware logic on the first portion of the streaming data, and (4) the resident hardware logic for the deactivated second area not performing the pipelined processing operations for that resident hardware logic on the first portion of the streaming data; and

selectively changing which areas of the FPGA are activated and deactivated when processing a different portion of the streaming data through the FPGA.

48. The method of claim 47 wherein the FPGA includes a pass through path for passing streaming data with respect to deactivated areas of the FPGA.

49. The method of claim 47 further comprising:

receiving the streaming data via a network interface.

50. The method of claim 49 wherein the FPGA and the network interface are part of a computer server.

51. The method of claim 50 wherein the computer server further comprises a processor, and wherein the FPGA offloads processing tasks from the processor.

52. The method of claim 51 further comprising:

the processor providing control instructions to the FPGA that are effective to activate and deactivate areas of the FPGA with respect to different portions of the streaming data.

53. The method of claim 51 wherein the FPGA further includes a control processor that manages a flow of streaming data to and from the resident hardware logic of the activated areas of the FPGA.

54. The method of claim 47 wherein the selectively changing step comprises:

for processing a second portion of the streaming data, (1) deactivating the first area of the FPGA, wherein the resident hardware logic for the deactivated first area remains resident on the FPGA while deactivated, (2) activating the second area of the FPGA, (3) the resident hardware logic for the activated second area performing the pipelined processing operations for that resident hardware logic on the second portion of the streaming data, and (4) the resident hardware logic for the deactivated first area not performing the pipelined processing operations for that resident hardware logic on the second portion of the streaming data.

55. The method of claim 47 wherein the activated first area includes resident hardware logic for an encryption engine.

56. The method of claim 55 wherein the encryption engine comprises a plurality of rounds that are fully pipelined.

57. The method of claim 55 wherein the deactivated second area includes resident hardware logic for a decryption engine.

58. The method of claim 47 wherein the activated first area includes resident hardware logic for an engine that computes a running aggregation of data within the first portion of the streaming data.

59. The method of claim 47 wherein the activated first area includes resident hardware logic for a decryption engine.

60. The method of claim 59 wherein the deactivated second area includes resident hardware logic for an encryption engine.

61. The method of claim 59 wherein the activated first area includes resident hardware logic for a search engine downstream from the decryption engine.

62. The method of claim 59 wherein the activated first area includes resident hardware logic for an encryption engine downstream from the decryption engine, and wherein the FPGA provides trans-encryption of the first portion of the streaming data via the decryption engine and the downstream encryption engine.

63. The method of claim 47 wherein the activated first area includes resident hardware logic for a compression engine.

64. The method of claim 47 wherein the activated first area includes resident hardware logic for a decompression engine.

65. The method of claim 47 wherein the activated first area includes resident hardware logic for a search engine.

66. The method of claim 47 wherein the activated first area includes resident hardware logic for pipelined processing of streaming DNA sequence data including matching operations on data within the streaming DNA sequence data.