Non-volatile storage with failure prediction

• US 10,346,232 B2
• Filed: 08/16/2017
• Issued: 07/09/2019
• Est. Priority Date: 08/16/2017
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Shulkin, Arthur, Rozman, David, Eliash, Tomer
• Primary Examiner(s): Bonzo, Bryce P
• Assistant Examiner(s): Arcos, Jeison C
• Application Number:
  US15/679,025
• Publication Number:
  US 20190056981A1
• Time in Patent Office: 692 Days
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles

Abstract

A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to collect failure bit counts (FBCs) for data read from the set of non-volatile memory cells, obtain one or more metrics of a cumulative distribution of the FBCs, calculate an indicator from the one or more metrics of the cumulative distribution of the FBCs and a target FBC, obtain a probability for the target FBC from the indicator, and manage at least one of: garbage collection, wear leveling, and read threshold voltage adjustment of the set of non-volatile memory cells according to the probability for the target FBC.

Claims

1. A non-volatile storage apparatus, comprising:

a set of non-volatile memory cells; and

one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to collect failure bit counts (FBCs) for data read from the set of non-volatile memory cells, obtain one or more metrics of a cumulative distribution of the FBCs, calculate an indicator from the one or more metrics of the cumulative distribution of the FBCs and a target FBC, obtain a probability for the target FBC from the indicator, and manage at least one of;

garbage collection, wear leveling, and read threshold voltage adjustment of the set of non-volatile memory cells according to the probability for the target FBC.

2. The non-volatile storage apparatus of claim 1 further comprising a table that links a plurality of indicator values with a plurality of probabilities, and wherein the one or more control circuits are configured to obtain the probability for the target FBC from the indicator according to the table.

3. The non-volatile storage apparatus of claim 2 wherein the plurality of probabilities are related to the indicator according to the equation:

4. The non-volatile storage apparatus of claim 3 wherein the one or more metrics of the cumulative distribution of the FBCs include the mean and standard deviation of the cumulative distribution of the FBCs and the indicator, z, is related to the mean and standard deviation of the cumulative distribution of the FBCs and the target FBC according to the equation:

5. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells form a non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate.

6. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells is comprised of a plurality of blocks of cells, a block of cells forming a minimum unit of erase, and wherein the one or more control circuits are further configured to manage operation of the plurality of blocks of cells according to a plurality of probabilities for the target FBC obtained for the plurality of blocks of cells.

7. The non-volatile storage apparatus of claim 6 wherein the one or more control circuits are configured to select blocks for garbage collection according to the plurality of probabilities for the target FBC obtained for the plurality of blocks of cells.

8. The non-volatile storage apparatus of claim 6 wherein the one or more control circuits are configured to select blocks for wear-leveling according to the probability for the target FBC obtained for the plurality of blocks of cells.

9. The non-volatile storage apparatus of claim 6 wherein the one or more control circuits are configured to adjust one or more voltages applied to a block of the plurality of blocks of cells according to the probability for the target FBC obtained for the block.

10. The non-volatile storage apparatus of claim 9 wherein the one or more control circuits are configured to adjust read threshold voltage of the block according to the probability for the target FBC obtained for the block.

11. The non-volatile storage apparatus of claim 6 wherein the one or more control circuits are configured to mark a block of the plurality of blocks of cells as unavailable for subsequent use according to the probability for the target FBC obtained for the block.

12. A method, comprising:

collecting failure bit counts (FBCs) for data read from a set of non-volatile memory cells;

obtaining one or more metrics of a distribution of the FBCs;

calculating an indicator from the one or more metrics of the distribution of the FBCs and a target FBC;

obtaining a probability for the target FBC from the indicator; and

performing at least one of;

garbage collection, wear leveling, and read threshold voltage adjustment, of the set of non-volatile memory cells according to the probability for the target FBC.

13. The method of claim 12 wherein obtaining the probability for the target FBC from the indicator includes looking up a table that links a plurality of indicator values with a plurality of probabilities.

14. The method of claim 12 wherein the distribution of the FBCs is a cumulative distribution function, the one or more metrics include a mean and standard deviation of the cumulative distribution function, and the indicator is related to the mean and standard deviation of the cumulative distribution of the FBCs and the target FBC according to the equation:

15. The method of claim 14 wherein the mean and standard deviation of the cumulative distribution of the FBCs are obtained for a number of FBCs that is less than one thousand and the probability for the target FBC is of the order of 10⁻

7.

16. The method of claim 12 further comprising managing the set of non-volatile memory cells according to a plurality of probabilities for the target FBC obtained for the set of non-volatile memory cells.

17. The method of claim 16 wherein managing the set of non-volatile memory cells includes performing at least one of:

garbage collection, wear leveling, and read threshold voltage adjustment, of the set of non-volatile memory cells according to the plurality of probabilities for the target FBC obtained for the plurality of blocks of cells.

18. The method of claim 16 wherein the set of non-volatile memory cells comprises a plurality of blocks, a block of cells forming a minimum unit of erase, and wherein managing the set of non-volatile memory cells includes identifying a block as a bad block that is subsequently unavailable for use according to the plurality of probabilities for the target FBC obtained for the set of non-volatile memory cells.

19. A system comprising:

a set of non-volatile memory cells;

means for collecting failure bit counts (FBCs) for data read from the set of non-volatile memory cells;

means for obtaining a mean and standard deviation of a cumulative distribution of the FBCs;

means for calculating an indicator from the mean and standard deviation of the cumulative distribution of the FBCs and a target FBC;

means for obtaining a probability for the target FBC from the indicator; and

means for operating the set of non-volatile memory cells according to the probability for the target FBC.

20. The system of claim 19 further comprising means for performing at least one of:

garbage collection, wear leveling, and read threshold voltage adjustment, of the set of non-volatile memory cells according to one or more probabilities obtained from one or more indicators.