Method and apparatus for bipolar memory write-verify

• US 10,347,314 B2
• Filed: 08/30/2017
• Issued: 07/09/2019
• Est. Priority Date: 08/14/2015
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Berger, Neal, Louie, Ben, El-Baraji, Mourad
• Primary Examiner(s): Yoha, Connie C
• Application Number:
  US15/691,577
• Publication Number:
  US 20170365317A1
• Time in Patent Office: 678 Days
• Field of Search: 365157, 365148, 365158, 36518522
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0066 Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing

Abstract

An advantageous write verify operation for bipolar memory devices is disclosed. The verify operation is performed under the same bias conditions as the write operation. Thus, the verify operation reduces disturb conditions caused when verify operation is performed in opposite bias to write operation. The advantageous write verify operation may be performed with control logic on source and bit lines. In another embodiment, the advantageous write operation is performed with mux coupled to control logic. The mux determines whether verify (0) or verify (1) operation should be performed based on data in a program latch. Moreover, the mux may select bias conditions for read operations based on a register bit. Trim circuits optionally provide guard banding and modify reference voltages for verify operations performed in opposite polarity to normal read operation.

Claims

1. An apparatus for writing data to a memory device, the apparatus comprising:

a memory cell coupled between a bit line and a source line, wherein the memory cell comprises a bipolar memory element and a select transistor;

wherein the bipolar memory element is operable to be coupled to the bit line; and

wherein the select transistor is operable to be coupled to the source line, and

wherein further the memory cell is operable to store a data bit of a write operation into the bipolar memory element responsive to application of a first differential voltage across the bit line and the source line to supply a current to write the data bit into the memory cell, wherein the first differential voltage comprises a first polarity if the data bit is a logic high, and wherein the first voltage differential comprises a second polarity if the data bit is a logic low and

wherein further the memory cell is operable to be read during a verification of the data bit responsive to an application of a second differential voltage across the bit line and the source line, wherein the second differential voltage is the first polarity if the data bit is a logic high, and wherein the second differential voltage is the second polarity if the data bit is a logic low.

2. The apparatus of claim 1, wherein the bipolar memory element is selected from a group consisting of:

a memresistor, chalcogenide glass, and a magnetic tunnel junction.

3. The apparatus of claim 1, further comprising:

a first bias circuit; and

a second bias circuit, wherein the first bias circuit is coupled to the source line and wherein the second bias circuit is coupled to the bit line and are operable to apply the first voltage differential.

4. The apparatus of claim 1, further comprising:

a first bias circuit; and

a second bias circuit, wherein the first bias circuit is coupled to the source line and wherein the second bias circuit is coupled to the bit line and are operable to apply the second differential voltage.

5. The apparatus of claim 1, further comprising:

a sense amplifier operable to detect a logic level corresponding to the data bit in the bipolar memory element prior to the verifying.

6. The apparatus of claim 1, further comprising:

a trim circuit operable to reduce the second differential voltage during the verification.

7. The apparatus of claim 1, further comprising:

a trim circuit operable to reduce an amount of time during which the second differential voltage is applied.

8. The apparatus of claim 7, wherein the second differential voltage is of opposite polarity to a voltage differential applied during a read operation.

9. The apparatus of claim 1, further comprising:

a program latch;

a multiplexer; and

a bias circuit, wherein the bias circuit is coupled to the multiplexer, wherein the multiplexer is coupled to the source line and the bit line, wherein the first voltage differential is applied with the bias circuit, and wherein the multiplexer is operable to drive a polarity of the first voltage differential based on a value of data in the program latch.

10. The apparatus of claim 1, further comprising:

a program latch;

a multiplexer; and

a bias circuit, wherein the bias circuit is coupled to the multiplexer, wherein the multiplexer is coupled to the source line and the bit line, wherein the second voltage differential is applied with the bias circuit, and wherein the multiplexer is operable to drive a polarity of the second voltage differential based on a value of data in the program latch.

11. The apparatus of claim 10, further comprising:

a sense amplifier, wherein the sense amplifier is coupled to the multiplexer, and wherein the sense amplifier is operable to detect a logic level corresponding to the data bit in the bipolar memory element.

12. An apparatus for writing data to a spin-transfer torque magnetic memory (STT-MRAM) device, said apparatus comprising:

a memory cell coupled between a bit line and a source line, wherein the memory cell comprises a bipolar memory element and a select transistor,

wherein further the memory cell is operable to store a data bit of a write operation into the bipolar memory element responsive to application of a first differential voltage across the bit line and the source line to supply a current to write the data bit into the memory cell, wherein the first differential voltage comprises a first polarity if the data bit is a logic high, and wherein the first voltage differential comprises a second polarity if the data bit is a logic low, and

wherein further the memory cell is operable to be read during a verification of the data bit responsive to an application of a second differential voltage across the bit line and the source line, wherein the second differential voltage is the first polarity if the data bit is a logic high, and wherein the second differential voltage is the second polarity if the data bit is a logic low.

13. The apparatus of claim 12, wherein the bipolar memory element operable to be coupled to the bit line, and wherein the select transistor operable to be coupled to the source line.

14. The apparatus of claim 12, wherein the bipolar memory element is selected from a group consisting of:

a memresistor, chalcogenide glass, and a magnetic tunnel junction.

15. The apparatus of claim 13, further comprising:

a first bias circuit; and

a second bias circuit, wherein the first bias circuit is coupled to the source line and wherein the second bias circuit is coupled to the bit line and are operable to apply the first voltage differential.

16. The apparatus of claim 13, further comprising:

a first bias circuit; and

a second bias circuit, wherein the first bias circuit is coupled to the source line and wherein the second bias circuit is coupled to the bit line and are operable to apply the second differential voltage.

17. The apparatus of claim 12, further comprising:

a sense amplifier operable to detect a logic level corresponding to the data bit in the bipolar memory element prior to the verifying.

18. The apparatus of claim 12, further comprising:

a trim circuit operable to reduce the second differential voltage during the verifying.

19. The apparatus of claim 12, further comprising:

a trim circuit operable to reduce an amount of time during which the second differential voltage is applied during the verification.

20. An apparatus for writing data to a memory device, the apparatus comprising:

a memory cell coupled between a bit line and a source line, wherein the memory cell comprises a bipolar memory element and a select transistor;

the bipolar memory element operable to be coupled to the bit line; and

the select transistor operable to be coupled to the source line,

wherein writing a data bit into the bipolar memory element of the memory cell comprises;

applying a first differential voltage bias across the bit line and the source line provided the data bit is a first logic value; and

applying a second differential voltage bias across the bit line and source line provided the data bit is a second logic value, wherein the second differential voltage bias is opposite in polarity to the first differential voltage bias; and

verifying the data bit of the memory cell, the verifying comprising;

reading the data bit of data from a latch; and

applying either the first or second differential voltage bias across the bit and the source line depending on the logic value of the data bit.

21. The apparatus of claim 20, wherein the applying of the verifying further comprises:

applying the first differential voltage bias across the bit and the source line provided the data bit is the first logic value; and

applying the second differential voltage bias across the bit and the source line provided the data bit is the second logic value.