Method and apparatus for bipolar memory write-verify
First Claim
1. An apparatus for writing data to a memory device, the apparatus comprising:
- a memory cell coupled between a bit line and a source line, wherein the memory cell comprises a bipolar memory element and a select transistor;
wherein the bipolar memory element is operable to be coupled to the bit line; and
wherein the select transistor is operable to be coupled to the source line, andwherein further the memory cell is operable to store a data bit of a write operation into the bipolar memory element responsive to application of a first differential voltage across the bit line and the source line to supply a current to write the data bit into the memory cell, wherein the first differential voltage comprises a first polarity if the data bit is a logic high, and wherein the first voltage differential comprises a second polarity if the data bit is a logic low andwherein further the memory cell is operable to be read during a verification of the data bit responsive to an application of a second differential voltage across the bit line and the source line, wherein the second differential voltage is the first polarity if the data bit is a logic high, and wherein the second differential voltage is the second polarity if the data bit is a logic low.
3 Assignments
0 Petitions
Accused Products
Abstract
An advantageous write verify operation for bipolar memory devices is disclosed. The verify operation is performed under the same bias conditions as the write operation. Thus, the verify operation reduces disturb conditions caused when verify operation is performed in opposite bias to write operation. The advantageous write verify operation may be performed with control logic on source and bit lines. In another embodiment, the advantageous write operation is performed with mux coupled to control logic. The mux determines whether verify (0) or verify (1) operation should be performed based on data in a program latch. Moreover, the mux may select bias conditions for read operations based on a register bit. Trim circuits optionally provide guard banding and modify reference voltages for verify operations performed in opposite polarity to normal read operation.
-
Citations
21 Claims
-
1. An apparatus for writing data to a memory device, the apparatus comprising:
-
a memory cell coupled between a bit line and a source line, wherein the memory cell comprises a bipolar memory element and a select transistor; wherein the bipolar memory element is operable to be coupled to the bit line; and wherein the select transistor is operable to be coupled to the source line, and wherein further the memory cell is operable to store a data bit of a write operation into the bipolar memory element responsive to application of a first differential voltage across the bit line and the source line to supply a current to write the data bit into the memory cell, wherein the first differential voltage comprises a first polarity if the data bit is a logic high, and wherein the first voltage differential comprises a second polarity if the data bit is a logic low and wherein further the memory cell is operable to be read during a verification of the data bit responsive to an application of a second differential voltage across the bit line and the source line, wherein the second differential voltage is the first polarity if the data bit is a logic high, and wherein the second differential voltage is the second polarity if the data bit is a logic low. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. An apparatus for writing data to a spin-transfer torque magnetic memory (STT-MRAM) device, said apparatus comprising:
-
a memory cell coupled between a bit line and a source line, wherein the memory cell comprises a bipolar memory element and a select transistor, wherein further the memory cell is operable to store a data bit of a write operation into the bipolar memory element responsive to application of a first differential voltage across the bit line and the source line to supply a current to write the data bit into the memory cell, wherein the first differential voltage comprises a first polarity if the data bit is a logic high, and wherein the first voltage differential comprises a second polarity if the data bit is a logic low, and wherein further the memory cell is operable to be read during a verification of the data bit responsive to an application of a second differential voltage across the bit line and the source line, wherein the second differential voltage is the first polarity if the data bit is a logic high, and wherein the second differential voltage is the second polarity if the data bit is a logic low. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
-
-
20. An apparatus for writing data to a memory device, the apparatus comprising:
-
a memory cell coupled between a bit line and a source line, wherein the memory cell comprises a bipolar memory element and a select transistor; the bipolar memory element operable to be coupled to the bit line; and the select transistor operable to be coupled to the source line, wherein writing a data bit into the bipolar memory element of the memory cell comprises; applying a first differential voltage bias across the bit line and the source line provided the data bit is a first logic value; and applying a second differential voltage bias across the bit line and source line provided the data bit is a second logic value, wherein the second differential voltage bias is opposite in polarity to the first differential voltage bias; and verifying the data bit of the memory cell, the verifying comprising; reading the data bit of data from a latch; and applying either the first or second differential voltage bias across the bit and the source line depending on the logic value of the data bit. - View Dependent Claims (21)
-
Specification