Group read refresh

• US 10,347,315 B2
• Filed: 10/31/2017
• Issued: 07/09/2019
• Est. Priority Date: 10/31/2017
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Reusswig, Philip David, Shah, Grishma, Yang, Nian Niles
• Primary Examiner(s): Le, Vu A
• Application Number:
  US15/800,023
• Publication Number:
  US 20190130964A1
• Time in Patent Office: 616 Days
• Field of Search: 365222, 36523003
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 29/783 with refresh of replacement cells, e.g. in DRAMs

Abstract

Apparatuses, systems, methods, and computer program products are disclosed for performing a group read refresh. An apparatus includes a plurality of memory groups. An apparatus includes an operation circuit that performs an operation on a selected memory group of a plurality of memory groups. An apparatus includes a remediation circuit that performs a countermeasure operation on an unselected memory group of a plurality of memory groups in response to an operation on a selected memory group.

Claims

1. An apparatus comprising:

a plurality of memory groups;

an operation circuit that performs an operation on a selected memory group of the plurality of memory groups, wherein the operation transitions the selected memory group to a read state; and

a remediation circuit that performs a countermeasure operation on an unselected memory group of the plurality of memory groups in response to the operation on the selected memory group, wherein the countermeasure operation places the unselected memory group into the read state.

2. The apparatus of claim 1, wherein the plurality of memory groups, the operation circuit, and the remediation circuit are part of a single integrated circuit chip.

3. The apparatus of claim 1, further comprising a control line circuit that provides a control voltage to the plurality of memory groups.

4. The apparatus of claim 3, wherein the control voltage opens a passing gate for each of the plurality of memory groups and the operation circuit provides the selected memory group an operation voltage for the operation and provides the unselected memory group a bias voltage during the operation, the bias voltage having a lower magnitude than the operation voltage.

5. The apparatus of claim 1, further comprising a row decoder shared by each memory group of the plurality of memory groups.

6. The apparatus of claim 1, wherein the remediation circuit performs the countermeasure operation on the unselected memory group without returning information stored on memory cells within the unselected memory group.

7. The apparatus of claim 1, wherein the operation circuit performing the operation on memory cells of the selected memory group puts the memory cells of the unselected memory group in a different read state than memory cells of the selected memory group.

8. The apparatus of claim 1, wherein the remediation circuit performs the countermeasure operation on the unselected memory group in response to detecting completion of the operation.

9. The apparatus of claim 1, wherein the remediation circuit performs the countermeasure operation on the unselected memory group in response to receiving a command to perform the countermeasure operation on the unselected memory group.

10. A system comprising:

a plurality of memory blocks coupled to the same control line;

a controller configured to;

perform an operation on a selected memory block of the plurality of memory blocks; and

as part of the operation, perform a read refresh on an unselected memory block of the plurality of memory blocks, wherein the read refresh puts the unselected memory block in a same read state as the selected memory block.

11. The system of claim 10, wherein the operation comprises one or more of an erase operation and a program operation.

12. The system of claim 10, wherein the read refresh comprises applying a read voltage to the unselected memory block without sensing data stored on the unselected memory block.

13. The system of claim 10, wherein an initial portion of the operation places the unselected memory block in a degraded read state, and the read refresh transitions the unselected memory block to a nominal read state.

14. The system of claim 10, wherein an initial portion of the operation places the selected memory block in a nominal read state.

15. The system of claim 10, wherein performing the read refresh on the unselected memory block comprises performing the read refresh on at least one page of the unselected memory block.

16. The system of claim 10, wherein performing the read refresh on the unselected memory block comprises applying a read voltage to the unselected memory block for a predetermined duration.

17. The system of claim 10, wherein performing the read refresh on the unselected memory block comprises waiting a predetermined duration prior to performing an operation on a memory block of the unselected memory block.

18. The system of claim 10, wherein the controller is configured to, as part of the operation, perform the read refresh on the selected memory block.

19. An apparatus comprising:

means for performing an operation on a selected group of memory cells of a plurality of memory cells using an operation voltage level for the selected group of memory cells and a different voltage level for an unselected group of memory cells of the plurality of memory cells, wherein the operation puts the unselected group of memory cells in a different read state than the selected group of memory cells; and

means for performing a read refresh on the unselected group of memory cells of the plurality of memory cells in response to completing the operation.