Resistive memory apparatus with a single read/write driver

• US 10,347,326 B2
• Filed: 08/09/2017
• Issued: 07/09/2019
• Est. Priority Date: 08/10/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Em, Ho Seok
• Primary Examiner(s): Siddique, Mushfique
• Application Number:
  US15/672,697
• Publication Number:
  US 20180047441A1
• Time in Patent Office: 699 Days
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A semiconductor memory apparatus includes a bias voltage generation circuit configured to generate a bias voltage according to a read voltage or a write voltage in response to a read signal and a write signal, a data discrimination circuit configured to generate a set enable signal and a reset enable signal in response to data and the write signal. The semiconductor memory apparatus also includes a current selection circuit configured to generate a first current in response to the read signal, the set enable signal, and the reset enable signal. The semiconductor memory apparatus further includes a driver configured to receive the first current and generate a second current in response to a voltage level of the bias voltage, and a first switch configured to provide the second current to a memory cell in response to the read signal and the write signal.

Claims

1. A semiconductor memory apparatus comprising:

a bias voltage generation circuit configured to generate a bias voltage according to a read voltage or a write voltage in response to a read signal and a write signal;

a data discrimination circuit configured to generate a set enable signal and a reset enable signal in response to data and the write signal;

a current selection circuit configured to generate a first current in response to the read signal, the set enable signal, and the reset enable signal;

a driver configured to receive the first current, and generate a second current in response to a voltage level of the bias voltage; and

a first switch configured to provide the second current to a memory cell in response to the read signal and the write signal,

wherein the bias voltage generation circuit includes a selection circuit configured to output the bias voltage as a feedback voltage when the read signal is enabled and output a voltage formed between the driver and the memory cell as the feedback voltage when the read signal is disabled.

2. The semiconductor memory apparatus according to claim 1, wherein:

the bias voltage generation circuit generates the bias voltage in response to a voltage level of the read voltage when the read signal is enabled; and

the bias voltage generation circuit generates the bias voltage when the write signal is enabled, such that the voltage formed between the driver and the first switch corresponds to a voltage level of the write voltage.

3. The semiconductor memory apparatus according to claim 1, wherein the bias voltage generation circuit comprises:

a reference voltage selection circuit configured to output one of the read voltage and the write voltage as a reference voltage in response to the read signal and the write signal;

a comparison circuit configured to compare voltage levels of the reference voltage and the feedback voltage, and generate the bias voltage.

4. The semiconductor memory apparatus according to claim 3, wherein the reference voltage selection circuit comprises:

a second switch configured to output the read voltage as the reference voltage when the read signal is enabled; and

a third switch configured to output the write voltage as the reference voltage when the write signal is enabled.

5. The semiconductor memory apparatus according to claim 1, wherein the data discrimination circuit enables one of the set enable signal and the reset enable signal depending on a level of the data when the write signal is enabled.

6. The semiconductor memory apparatus according to claim 5, wherein the data discrimination circuit disables both the set enable signal and the reset enable signal regardless of the data when the write signal is disabled.

7. The semiconductor memory apparatus according to claim 1, wherein:

the current selection circuit outputs the first current having a current amount corresponding to a read current when the read signal is enabled;

the current selection circuit outputs the first current having a current amount corresponding to a set current when the set enable signal is enabled; and

the current selection circuit outputs the first current having a current amount corresponding to a reset current when the reset enable signal is enabled.

8. The semiconductor memory apparatus according to claim 7, wherein the current selection circuit comprises:

a current mirror circuit configured to output the first current having a current amount corresponding to an amount of a current which flows out from a node;

a read current circuit configured to cause the read current to flow from the node to a ground terminal when the read signal is enabled;

a set current circuit configured to cause the set current to flow from the node to the ground terminal when the set enable signal is enabled; and

a reset current circuit configured to cause the reset current to flow from the node to the ground terminal when the reset enable signal is enabled.

9. The semiconductor memory apparatus according to claim 1, wherein the first switch is turned on when either one of the read signal and the write signal is enabled, and transfers the second current to the memory cell.

10. The semiconductor memory apparatus according to claim 9, wherein a current sink circuit allows the second current to flow from the memory cell to a ground terminal.

11. The semiconductor memory apparatus according to claim 1, wherein the second current generated by the driver corresponds to the voltage level of the bias voltage.

12. A semiconductor memory apparatus comprising:

a driver configured to generate a current corresponding to a voltage level of a bias voltage, and provide the current to a memory cell;

a reference voltage selection circuit configured to output one of a read voltage and a write voltage as a reference voltage in response to a read signal and a write signal;

a comparison circuit configured to compare voltage levels of the reference voltage and a feedback voltage, and generate the bias voltage; and

a selection circuit configured to output the bias voltage as the feedback voltage when the read signal is enabled and output a voltage formed between the driver and the memory cell as the feedback voltage when the read signal is disabled.

13. The semiconductor memory apparatus according to claim 12, wherein:

the reference voltage selection circuit outputs the read voltage as the reference voltage when the read signal is enabled; and

the reference voltage selection circuit outputs the write voltage as the reference voltage when the write signal is enabled.

14. The semiconductor memory apparatus according to claim 12, further comprising:

a data discrimination circuit configured to generate a set enable signal and a reset enable signal in response to the write signal and data; and

a current selection circuit configured to provide a current having a current amount corresponding to each of the read signal, the set enable signal and the reset enable signal, to the driver.

15. The semiconductor memory apparatus according to claim 14, wherein the data discrimination circuit enables one of the set enable signal and the reset enable signal in response to a level of the data when the write signal is enabled.

16. The semiconductor memory apparatus according to claim 14, wherein:

the current selection circuit generates a current having a current amount corresponding to a read current when the read signal is enabled;

the current selection circuit generates a current having a current amount corresponding to a set current when the set enable signal is enabled; and

the current selection circuit generates a current having a current amount corresponding to a reset current when the reset enable signal is enabled.

17. The semiconductor memory apparatus according to claim 14, wherein the current selection circuit comprises:

a current mirror circuit configured to output a current having a current amount corresponding to an amount of current which flows out from a node;

a read current circuit configured to cause the read current to flow from the node to a ground terminal when the read signal is enabled;

a set current circuit configured to cause the set current to flow from the node to the ground terminal when the set enable signal is enabled; and

a reset current circuit configured to cause the reset current to flow from the node to the ground terminal when the reset enable signal is enabled.

18. The semiconductor memory apparatus according to claim 12 wherein the driver is configured to provide the current to the memory cell via a switch.

19. The semiconductor memory apparatus according to claim 18, wherein the switch is turned on when either one of the read signal and the write signal is enabled, and the switch transfers the current to the memory cell.