Resistive memory apparatus with a single read/write driver
First Claim
1. A semiconductor memory apparatus comprising:
- a bias voltage generation circuit configured to generate a bias voltage according to a read voltage or a write voltage in response to a read signal and a write signal;
a data discrimination circuit configured to generate a set enable signal and a reset enable signal in response to data and the write signal;
a current selection circuit configured to generate a first current in response to the read signal, the set enable signal, and the reset enable signal;
a driver configured to receive the first current, and generate a second current in response to a voltage level of the bias voltage; and
a first switch configured to provide the second current to a memory cell in response to the read signal and the write signal,wherein the bias voltage generation circuit includes a selection circuit configured to output the bias voltage as a feedback voltage when the read signal is enabled and output a voltage formed between the driver and the memory cell as the feedback voltage when the read signal is disabled.
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Abstract
A semiconductor memory apparatus includes a bias voltage generation circuit configured to generate a bias voltage according to a read voltage or a write voltage in response to a read signal and a write signal, a data discrimination circuit configured to generate a set enable signal and a reset enable signal in response to data and the write signal. The semiconductor memory apparatus also includes a current selection circuit configured to generate a first current in response to the read signal, the set enable signal, and the reset enable signal. The semiconductor memory apparatus further includes a driver configured to receive the first current and generate a second current in response to a voltage level of the bias voltage, and a first switch configured to provide the second current to a memory cell in response to the read signal and the write signal.
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Citations
19 Claims
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1. A semiconductor memory apparatus comprising:
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a bias voltage generation circuit configured to generate a bias voltage according to a read voltage or a write voltage in response to a read signal and a write signal; a data discrimination circuit configured to generate a set enable signal and a reset enable signal in response to data and the write signal; a current selection circuit configured to generate a first current in response to the read signal, the set enable signal, and the reset enable signal; a driver configured to receive the first current, and generate a second current in response to a voltage level of the bias voltage; and a first switch configured to provide the second current to a memory cell in response to the read signal and the write signal, wherein the bias voltage generation circuit includes a selection circuit configured to output the bias voltage as a feedback voltage when the read signal is enabled and output a voltage formed between the driver and the memory cell as the feedback voltage when the read signal is disabled. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor memory apparatus comprising:
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a driver configured to generate a current corresponding to a voltage level of a bias voltage, and provide the current to a memory cell; a reference voltage selection circuit configured to output one of a read voltage and a write voltage as a reference voltage in response to a read signal and a write signal; a comparison circuit configured to compare voltage levels of the reference voltage and a feedback voltage, and generate the bias voltage; and a selection circuit configured to output the bias voltage as the feedback voltage when the read signal is enabled and output a voltage formed between the driver and the memory cell as the feedback voltage when the read signal is disabled. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification